Searched hist:cba71b70ef7070bcd38a8d202f30e58f79e36c6b (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a35.h | cba71b70ef7070bcd38a8d202f30e58f79e36c6b Fri Apr 05 15:25:25 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Cortex-A35: Implement workaround for errata 855472
Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.
Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a35.S | cba71b70ef7070bcd38a8d202f30e58f79e36c6b Fri Apr 05 15:25:25 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Cortex-A35: Implement workaround for errata 855472
Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.
Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | cba71b70ef7070bcd38a8d202f30e58f79e36c6b Fri Apr 05 15:25:25 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Cortex-A35: Implement workaround for errata 855472
Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.
Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|