1820756e9SSandrine Bailleux /* 2*a727d59dSJacky Bai * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. 3820756e9SSandrine Bailleux * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5820756e9SSandrine Bailleux */ 6820756e9SSandrine Bailleux 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A35_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A35_H 9820756e9SSandrine Bailleux 101a74e4a8SAntonio Nino Diaz #include <lib/utils_def.h> 111a74e4a8SAntonio Nino Diaz 12820756e9SSandrine Bailleux /* Cortex-A35 Main ID register for revision 0 */ 131a74e4a8SAntonio Nino Diaz #define CORTEX_A35_MIDR U(0x410FD040) 14820756e9SSandrine Bailleux 15*a727d59dSJacky Bai /* L2 Extended Control Register */ 16*a727d59dSJacky Bai #define CORTEX_A35_L2ECTLR_EL1 S3_1_C11_C0_3 17*a727d59dSJacky Bai 18820756e9SSandrine Bailleux /******************************************************************************* 19820756e9SSandrine Bailleux * CPU Extended Control register specific definitions. 20820756e9SSandrine Bailleux * CPUECTLR_EL1 is an implementation-specific register. 21820756e9SSandrine Bailleux ******************************************************************************/ 22820756e9SSandrine Bailleux #define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1 231a74e4a8SAntonio Nino Diaz #define CORTEX_A35_CPUECTLR_SMPEN_BIT (ULL(1) << 6) 24820756e9SSandrine Bailleux 25cba71b70SLouis Mayencourt /******************************************************************************* 26cba71b70SLouis Mayencourt * CPU Auxiliary Control register specific definitions. 27cba71b70SLouis Mayencourt ******************************************************************************/ 28cba71b70SLouis Mayencourt #define CORTEX_A35_CPUACTLR_EL1 S3_1_C15_C2_0 29cba71b70SLouis Mayencourt 30cba71b70SLouis Mayencourt #define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI (ULL(1) << 44) 31cba71b70SLouis Mayencourt 32c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A35_H */ 33