Searched hist:c72f4d4c2ebb3be9797ef6cd7dcbc2124c825f7a (Results 1 – 5 of 5) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/ |
| H A D | pll-ld11.c | c72f4d4c2ebb3be9797ef6cd7dcbc2124c825f7a Wed Sep 21 22:42:19 UTC 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| H A D | Makefile | c72f4d4c2ebb3be9797ef6cd7dcbc2124c825f7a Wed Sep 21 22:42:19 UTC 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| /rk3399_rockchip-uboot/arch/arm/mach-uniphier/ |
| H A D | sc64-regs.h | c72f4d4c2ebb3be9797ef6cd7dcbc2124c825f7a Wed Sep 21 22:42:19 UTC 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| H A D | board_init.c | c72f4d4c2ebb3be9797ef6cd7dcbc2124c825f7a Wed Sep 21 22:42:19 UTC 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| H A D | init.h | c72f4d4c2ebb3be9797ef6cd7dcbc2124c825f7a Wed Sep 21 22:42:19 UTC 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|