| #
e4adc8ed |
| 01-Sep-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-uniphier
- add {ofnode,dev}_read_resource_byname - provide DT probe hook to Denali NAND driver - update clk/reset driver - update DT - misc cleanups
|
| #
a55957b9 |
| 26-Aug-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: move PLLCTRL register macros to each SoC .c file
The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Mo
ARM: uniphier: move PLLCTRL register macros to each SoC .c file
The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Move them to per-SoC .c file. Also, fix some PLL comments.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| #
9f375f65 |
| 29-Oct-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-uniphier
|
| #
76466bd7 |
| 27-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabled
At the moment, the clk driver is not clever enough to automatically enable parent clocks like Linux. Enable the STDMAC clock exp
ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabled
At the moment, the clk driver is not clever enough to automatically enable parent clocks like Linux. Enable the STDMAC clock explicitly if USB is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| #
68ff827e |
| 18-Oct-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-uniphier
|
| #
0bd203bb |
| 12-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: fix addresses of Cortex-A72 gear setting macros
My mistake during copy-paste work.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| #
231af7f9 |
| 22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-uniphier
|
| #
c72f4d4c |
| 21-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set t
ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| #
9a6535e0 |
| 18-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-uniphier
|
| #
682e09ff |
| 16-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: add PLL init code for LD20 SoC
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use.
Signed-off-by: M
ARM: uniphier: add PLL init code for LD20 SoC
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| #
650aedbf |
| 18-Mar-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: add System Control register macros for ARMv8 SoCs
The System Control block moved to a completely different register map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones
ARM: uniphier: add System Control register macros for ARMv8 SoCs
The System Control block moved to a completely different register map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones. Define register macros in a new header file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|