Searched hist:c0cbf5ad6e5d6ef6ee43f6e926e1d9f7a488b451 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/drivers/nxp/clk/s32cc/ |
| H A D | s32cc-clk-drv.h | c0cbf5ad6e5d6ef6ee43f6e926e1d9f7a488b451 Wed Oct 01 11:02:17 UTC 2025 Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> feat(s32g274ardb): add DDR clock source support
Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.
These utilities are required before
initializing the DDR subsystem.
Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
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| /rk3399_ARM-atf/drivers/nxp/clk/s32cc/include/ |
| H A D | s32cc-mc-rgm.h | c0cbf5ad6e5d6ef6ee43f6e926e1d9f7a488b451 Wed Oct 01 11:02:17 UTC 2025 Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> feat(s32g274ardb): add DDR clock source support
Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.
These utilities are required before
initializing the DDR subsystem.
Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
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| /rk3399_ARM-atf/drivers/nxp/clk/s32cc/ |
| H A D | mc_rgm.c | c0cbf5ad6e5d6ef6ee43f6e926e1d9f7a488b451 Wed Oct 01 11:02:17 UTC 2025 Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> feat(s32g274ardb): add DDR clock source support
Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.
These utilities are required before
initializing the DDR subsystem.
Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
|
| H A D | s32cc_early_clks.c | c0cbf5ad6e5d6ef6ee43f6e926e1d9f7a488b451 Wed Oct 01 11:02:17 UTC 2025 Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> feat(s32g274ardb): add DDR clock source support
Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.
These utilities are required before
initializing the DDR subsystem.
Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
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