| #
8f64ed92 |
| 30-Oct-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "upstream_deassert_ddr_reset" into integration
* changes:
feat(s32g274ardb): add DDR clock source support
feat(s32g274ardb): add mc_rgm_release_periph func
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| #
c0cbf5ad |
| 01-Oct-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
feat(s32g274ardb): add DDR clock source support
Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.
These utilities are required before
i
feat(s32g274ardb): add DDR clock source support
Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.
These utilities are required before
initializing the DDR subsystem.
Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
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|
| #
624ffe51 |
| 14-Jan-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "nxp-s32g274a/enable-mmu" into integration
* changes:
feat(s32g274a): split early clock initialization
feat(s32g274a): enable MMU for BL31 stage
feat(s32g274a): dynami
Merge changes from topic "nxp-s32g274a/enable-mmu" into integration
* changes:
feat(s32g274a): split early clock initialization
feat(s32g274a): enable MMU for BL31 stage
feat(s32g274a): dynamically map GIC regions
feat(s32g274a): enable MMU for BL2 stage
feat(s32g274a): dynamically map siul2 and fip img
feat(s32g274a): map each image before its loading
feat(nxp-clk): dynamic map of the clock modules
feat(s32g274a): increase the number of MMU regions
feat(s32g274a): add console mapping
show more ...
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| #
61b5ef21 |
| 27-Nov-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(s32g274a): split early clock initialization
Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks ca
feat(s32g274a): split early clock initialization
Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.
Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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|
| #
638e3aa5 |
| 05-Jul-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "add_s32cc_fxosc_clk" into integration
* changes:
feat(s32g274a): enable BL2 early clocks
feat(nxp-clk): implement set_rate for oscillators
feat(nxp-clk): add oscillat
Merge changes from topic "add_s32cc_fxosc_clk" into integration
* changes:
feat(s32g274a): enable BL2 early clocks
feat(nxp-clk): implement set_rate for oscillators
feat(nxp-clk): add oscillator clock objects
feat(nxp-clk): add minimal set of S32CC clock ids
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| #
66af5425 |
| 12-Jun-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(s32g274a): enable BL2 early clocks
s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and L
feat(s32g274a): enable BL2 early clocks
s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and Linflex clocks. For now, it will only contain the
frequency set for FXOSC. More clock management will be added in the next
commits.
Change-Id: Ie85465884de02f5082185f91749f190f40249c2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
show more ...
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