Searched hist:b4017364630fbc526bbf5e917d8fae6013805488 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | soc.h | b4017364630fbc526bbf5e917d8fae6013805488 Thu Nov 05 06:30:14 UTC 2015 Prabhakar Kushwaha <prabhakar@freescale.com> armv8: ls2085a: Add workaround of errata A009635
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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| H A D | config.h | b4017364630fbc526bbf5e917d8fae6013805488 Thu Nov 05 06:30:14 UTC 2015 Prabhakar Kushwaha <prabhakar@freescale.com> armv8: ls2085a: Add workaround of errata A009635
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | soc.c | b4017364630fbc526bbf5e917d8fae6013805488 Thu Nov 05 06:30:14 UTC 2015 Prabhakar Kushwaha <prabhakar@freescale.com> armv8: ls2085a: Add workaround of errata A009635
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
| H A D | cpu.c | b4017364630fbc526bbf5e917d8fae6013805488 Thu Nov 05 06:30:14 UTC 2015 Prabhakar Kushwaha <prabhakar@freescale.com> armv8: ls2085a: Add workaround of errata A009635
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|