Searched hist:ae6c7c97d4e0f491854b34628e0fa1038668f8e4 (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_x2.h | ae6c7c97d4e0f491854b34628e0fa1038668f8e4 Wed Jan 22 00:02:51 UTC 2025 Govindraj Raja <govindraj.raja@arm.com> fix(cpus): workaround for Cortex-X2 erratum 3701772
Cortex-X2 erratum 3701772 that applies to r0p0, r1p0, r2p0, r2p1
is still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest/
Change-Id: I2ffc5e7d7467f1bcff8b895fea52a1daa7d14495
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | errata_common.c | ae6c7c97d4e0f491854b34628e0fa1038668f8e4 Wed Jan 22 00:02:51 UTC 2025 Govindraj Raja <govindraj.raja@arm.com> fix(cpus): workaround for Cortex-X2 erratum 3701772
Cortex-X2 erratum 3701772 that applies to r0p0, r1p0, r2p0, r2p1
is still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest/
Change-Id: I2ffc5e7d7467f1bcff8b895fea52a1daa7d14495
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|
| H A D | cpu-ops.mk | ae6c7c97d4e0f491854b34628e0fa1038668f8e4 Wed Jan 22 00:02:51 UTC 2025 Govindraj Raja <govindraj.raja@arm.com> fix(cpus): workaround for Cortex-X2 erratum 3701772
Cortex-X2 erratum 3701772 that applies to r0p0, r1p0, r2p0, r2p1
is still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest/
Change-Id: I2ffc5e7d7467f1bcff8b895fea52a1daa7d14495
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_x2.S | ae6c7c97d4e0f491854b34628e0fa1038668f8e4 Wed Jan 22 00:02:51 UTC 2025 Govindraj Raja <govindraj.raja@arm.com> fix(cpus): workaround for Cortex-X2 erratum 3701772
Cortex-X2 erratum 3701772 that applies to r0p0, r1p0, r2p0, r2p1
is still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest/
Change-Id: I2ffc5e7d7467f1bcff8b895fea52a1daa7d14495
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | ae6c7c97d4e0f491854b34628e0fa1038668f8e4 Wed Jan 22 00:02:51 UTC 2025 Govindraj Raja <govindraj.raja@arm.com> fix(cpus): workaround for Cortex-X2 erratum 3701772
Cortex-X2 erratum 3701772 that applies to r0p0, r1p0, r2p0, r2p1
is still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest/
Change-Id: I2ffc5e7d7467f1bcff8b895fea52a1daa7d14495
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|