| /rk3399_rockchip-uboot/board/socrates/ |
| H A D | socrates.c | a5d212a263c58cc746481bf1fc878510533ce7d6 Wed Dec 03 23:16:34 UTC 2008 Trent Piepho <tpiepho@freescale.com> mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
|
| /rk3399_rockchip-uboot/board/freescale/mpc8541cds/ |
| H A D | mpc8541cds.c | a5d212a263c58cc746481bf1fc878510533ce7d6 Wed Dec 03 23:16:34 UTC 2008 Trent Piepho <tpiepho@freescale.com> mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
|
| /rk3399_rockchip-uboot/board/freescale/mpc8555cds/ |
| H A D | mpc8555cds.c | a5d212a263c58cc746481bf1fc878510533ce7d6 Wed Dec 03 23:16:34 UTC 2008 Trent Piepho <tpiepho@freescale.com> mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
|
| /rk3399_rockchip-uboot/board/freescale/mpc8568mds/ |
| H A D | mpc8568mds.c | a5d212a263c58cc746481bf1fc878510533ce7d6 Wed Dec 03 23:16:34 UTC 2008 Trent Piepho <tpiepho@freescale.com> mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
|
| /rk3399_rockchip-uboot/board/freescale/mpc8548cds/ |
| H A D | mpc8548cds.c | a5d212a263c58cc746481bf1fc878510533ce7d6 Wed Dec 03 23:16:34 UTC 2008 Trent Piepho <tpiepho@freescale.com> mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
|
| /rk3399_rockchip-uboot/board/sbc8548/ |
| H A D | sbc8548.c | a5d212a263c58cc746481bf1fc878510533ce7d6 Wed Dec 03 23:16:34 UTC 2008 Trent Piepho <tpiepho@freescale.com> mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
|