| /optee_os/core/arch/arm/cpu/ |
| H A D | cortex-a35.mk | a4ca182ffda9dd1515a90f16f820829b46e52a96 Tue Nov 11 08:09:40 UTC 2025 Hugues KAMBA MPIANA <hugues.kambampiana@arm.com> plat-corstone1000: Add Cortex-A320 support
Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the make command line.
The Cortex-A320 core is not yet supported via -mcpu=cortex-a320.
When arm64-platform-cpuarch is set to cortex-a320, switch to
-march=armv9.2-a.
The new Corstone-1000 variant with Cortex-A320 replaces the original
GIC-400 (v2) interrupt controller with a GIC-600, which is
architecturally compliant with GICv3. Since OP-TEE already provides
a generic GICv3 driver, only minimal platform changes are needed
to expose the updated register map and initialize the GICv3 interface.
**Changes introduced**
* When `cortex-a320` is selected:
* Force `CFG_ARM_GICV3=y`.
* Map the Redistributor region (`GICR_BASE`).
* Use `gic_init_v3(…)` instead of the v2 helper for Cortex-A320 builds.
* Add `GICR_BASE`, `GIC_REDIST_REG_SIZE`, and related offsets.
* Retain legacy `GICC_BASE` definitions under the GICv2 path so that
the Cortex-A35 + GIC-400 variant continues to build unchanged.
Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | cortex-a320.mk | a4ca182ffda9dd1515a90f16f820829b46e52a96 Tue Nov 11 08:09:40 UTC 2025 Hugues KAMBA MPIANA <hugues.kambampiana@arm.com> plat-corstone1000: Add Cortex-A320 support
Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the make command line.
The Cortex-A320 core is not yet supported via -mcpu=cortex-a320.
When arm64-platform-cpuarch is set to cortex-a320, switch to
-march=armv9.2-a.
The new Corstone-1000 variant with Cortex-A320 replaces the original
GIC-400 (v2) interrupt controller with a GIC-600, which is
architecturally compliant with GICv3. Since OP-TEE already provides
a generic GICv3 driver, only minimal platform changes are needed
to expose the updated register map and initialize the GICv3 interface.
**Changes introduced**
* When `cortex-a320` is selected:
* Force `CFG_ARM_GICV3=y`.
* Map the Redistributor region (`GICR_BASE`).
* Use `gic_init_v3(…)` instead of the v2 helper for Cortex-A320 builds.
* Add `GICR_BASE`, `GIC_REDIST_REG_SIZE`, and related offsets.
* Retain legacy `GICC_BASE` definitions under the GICv2 path so that
the Cortex-A35 + GIC-400 variant continues to build unchanged.
Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | cortex-armv8-0.mk | a4ca182ffda9dd1515a90f16f820829b46e52a96 Tue Nov 11 08:09:40 UTC 2025 Hugues KAMBA MPIANA <hugues.kambampiana@arm.com> plat-corstone1000: Add Cortex-A320 support
Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the make command line.
The Cortex-A320 core is not yet supported via -mcpu=cortex-a320.
When arm64-platform-cpuarch is set to cortex-a320, switch to
-march=armv9.2-a.
The new Corstone-1000 variant with Cortex-A320 replaces the original
GIC-400 (v2) interrupt controller with a GIC-600, which is
architecturally compliant with GICv3. Since OP-TEE already provides
a generic GICv3 driver, only minimal platform changes are needed
to expose the updated register map and initialize the GICv3 interface.
**Changes introduced**
* When `cortex-a320` is selected:
* Force `CFG_ARM_GICV3=y`.
* Map the Redistributor region (`GICR_BASE`).
* Use `gic_init_v3(…)` instead of the v2 helper for Cortex-A320 builds.
* Add `GICR_BASE`, `GIC_REDIST_REG_SIZE`, and related offsets.
* Retain legacy `GICC_BASE` definitions under the GICv2 path so that
the Cortex-A35 + GIC-400 variant continues to build unchanged.
Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/arch/arm/plat-corstone1000/ |
| H A D | platform_config.h | a4ca182ffda9dd1515a90f16f820829b46e52a96 Tue Nov 11 08:09:40 UTC 2025 Hugues KAMBA MPIANA <hugues.kambampiana@arm.com> plat-corstone1000: Add Cortex-A320 support
Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the make command line.
The Cortex-A320 core is not yet supported via -mcpu=cortex-a320.
When arm64-platform-cpuarch is set to cortex-a320, switch to
-march=armv9.2-a.
The new Corstone-1000 variant with Cortex-A320 replaces the original
GIC-400 (v2) interrupt controller with a GIC-600, which is
architecturally compliant with GICv3. Since OP-TEE already provides
a generic GICv3 driver, only minimal platform changes are needed
to expose the updated register map and initialize the GICv3 interface.
**Changes introduced**
* When `cortex-a320` is selected:
* Force `CFG_ARM_GICV3=y`.
* Map the Redistributor region (`GICR_BASE`).
* Use `gic_init_v3(…)` instead of the v2 helper for Cortex-A320 builds.
* Add `GICR_BASE`, `GIC_REDIST_REG_SIZE`, and related offsets.
* Retain legacy `GICC_BASE` definitions under the GICv2 path so that
the Cortex-A35 + GIC-400 variant continues to build unchanged.
Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | conf.mk | a4ca182ffda9dd1515a90f16f820829b46e52a96 Tue Nov 11 08:09:40 UTC 2025 Hugues KAMBA MPIANA <hugues.kambampiana@arm.com> plat-corstone1000: Add Cortex-A320 support
Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the make command line.
The Cortex-A320 core is not yet supported via -mcpu=cortex-a320.
When arm64-platform-cpuarch is set to cortex-a320, switch to
-march=armv9.2-a.
The new Corstone-1000 variant with Cortex-A320 replaces the original
GIC-400 (v2) interrupt controller with a GIC-600, which is
architecturally compliant with GICv3. Since OP-TEE already provides
a generic GICv3 driver, only minimal platform changes are needed
to expose the updated register map and initialize the GICv3 interface.
**Changes introduced**
* When `cortex-a320` is selected:
* Force `CFG_ARM_GICV3=y`.
* Map the Redistributor region (`GICR_BASE`).
* Use `gic_init_v3(…)` instead of the v2 helper for Cortex-A320 builds.
* Add `GICR_BASE`, `GIC_REDIST_REG_SIZE`, and related offsets.
* Retain legacy `GICC_BASE` definitions under the GICv2 path so that
the Cortex-A35 + GIC-400 variant continues to build unchanged.
Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | main.c | a4ca182ffda9dd1515a90f16f820829b46e52a96 Tue Nov 11 08:09:40 UTC 2025 Hugues KAMBA MPIANA <hugues.kambampiana@arm.com> plat-corstone1000: Add Cortex-A320 support
Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the make command line.
The Cortex-A320 core is not yet supported via -mcpu=cortex-a320.
When arm64-platform-cpuarch is set to cortex-a320, switch to
-march=armv9.2-a.
The new Corstone-1000 variant with Cortex-A320 replaces the original
GIC-400 (v2) interrupt controller with a GIC-600, which is
architecturally compliant with GICv3. Since OP-TEE already provides
a generic GICv3 driver, only minimal platform changes are needed
to expose the updated register map and initialize the GICv3 interface.
**Changes introduced**
* When `cortex-a320` is selected:
* Force `CFG_ARM_GICV3=y`.
* Map the Redistributor region (`GICR_BASE`).
* Use `gic_init_v3(…)` instead of the v2 helper for Cortex-A320 builds.
* Add `GICR_BASE`, `GIC_REDIST_REG_SIZE`, and related offsets.
* Retain legacy `GICC_BASE` definitions under the GICv2 path so that
the Cortex-A35 + GIC-400 variant continues to build unchanged.
Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|