| #
a4ca182f |
| 11-Nov-2025 |
Hugues KAMBA MPIANA <hugues.kambampiana@arm.com> |
plat-corstone1000: Add Cortex-A320 support
Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the
plat-corstone1000: Add Cortex-A320 support
Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the make command line.
The Cortex-A320 core is not yet supported via -mcpu=cortex-a320.
When arm64-platform-cpuarch is set to cortex-a320, switch to
-march=armv9.2-a.
The new Corstone-1000 variant with Cortex-A320 replaces the original
GIC-400 (v2) interrupt controller with a GIC-600, which is
architecturally compliant with GICv3. Since OP-TEE already provides
a generic GICv3 driver, only minimal platform changes are needed
to expose the updated register map and initialize the GICv3 interface.
**Changes introduced**
* When `cortex-a320` is selected:
* Force `CFG_ARM_GICV3=y`.
* Map the Redistributor region (`GICR_BASE`).
* Use `gic_init_v3(…)` instead of the v2 helper for Cortex-A320 builds.
* Add `GICR_BASE`, `GIC_REDIST_REG_SIZE`, and related offsets.
* Retain legacy `GICC_BASE` definitions under the GICv2 path so that
the Cortex-A35 + GIC-400 variant continues to build unchanged.
Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| #
55544d37 |
| 03-Jul-2025 |
Frazer Carsley <frazer.carsley@arm.com> |
plat-corstone1000: increase CFG_TZDRAM_SIZE
TZDRAM is a 4MB SRAM in Corstone-1000. Its start address is `0x0200_0000`
but the first 0x2000 bytes are reserved for future use. `CFG_TZDRAM_SIZE`
can be
plat-corstone1000: increase CFG_TZDRAM_SIZE
TZDRAM is a 4MB SRAM in Corstone-1000. Its start address is `0x0200_0000`
but the first 0x2000 bytes are reserved for future use. `CFG_TZDRAM_SIZE`
can be increased to `0x360000` so OP-TEE has more RAM.
Signed-off-by: Bence Balogh <bence.balogh@arm.com>
Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| #
258b72d2 |
| 31-Jul-2024 |
Ali Can Ozaslan <ali.oezaslan@arm.com> |
core: plat-corstone1000: Increase TZDRAM size
Increased TZDRAM size using space.
NS_SHARED_RAM region is not used by Corstone1000 platform. It is
removed to create more space in secure RAM for BL32
core: plat-corstone1000: Increase TZDRAM size
Increased TZDRAM size using space.
NS_SHARED_RAM region is not used by Corstone1000 platform. It is
removed to create more space in secure RAM for BL32 image.
Thus, there is more space in the secure RAM that can be used by OP-TEE.
Signed-off-by: Ali Can Ozaslan <ali.oezaslan@arm.com>
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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|
| #
42f66171 |
| 22-Jun-2021 |
Vishnu Banavath <vishnu.banavath@arm.com> |
plat-corstone1000: add corstone1000 platform
These changes are to add corstone1000 platform to optee
core.
arch/arm/plat-vexpress is taken as a reference to make
these changes.
Signed-off-by: Vishn
plat-corstone1000: add corstone1000 platform
These changes are to add corstone1000 platform to optee
core.
arch/arm/plat-vexpress is taken as a reference to make
these changes.
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|