Searched hist:a45526aaa0ae241f3e1df996fed988a014eeffe8 (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/ |
| H A D | wrap_pll_config.c | a45526aaa0ae241f3e1df996fed988a014eeffe8 Tue Jan 31 18:33:08 UTC 2017 Dinh Nguyen <dinguyen@kernel.org> arm: socfpga: set the mpuclk divider in the Altera group register
The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pll.
Without this patch, the default value of the register is 1, so the mpuclk
will always get divided by 2 if the correct value is not set. For example,
on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
1.05 GHz.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
|
| H A D | clock_manager.c | a45526aaa0ae241f3e1df996fed988a014eeffe8 Tue Jan 31 18:33:08 UTC 2017 Dinh Nguyen <dinguyen@kernel.org> arm: socfpga: set the mpuclk divider in the Altera group register
The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pll.
Without this patch, the default value of the register is 1, so the mpuclk
will always get divided by 2 if the correct value is not set. For example,
on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
1.05 GHz.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
|
| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/include/mach/ |
| H A D | clock_manager.h | a45526aaa0ae241f3e1df996fed988a014eeffe8 Tue Jan 31 18:33:08 UTC 2017 Dinh Nguyen <dinguyen@kernel.org> arm: socfpga: set the mpuclk divider in the Altera group register
The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pll.
Without this patch, the default value of the register is 1, so the mpuclk
will always get divided by 2 if the correct value is not set. For example,
on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
1.05 GHz.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
|