| #
a45526aa |
| 31-Jan-2017 |
Dinh Nguyen <dinguyen@kernel.org> |
arm: socfpga: set the mpuclk divider in the Altera group register
The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pl
arm: socfpga: set the mpuclk divider in the Altera group register
The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pll.
Without this patch, the default value of the register is 1, so the mpuclk
will always get divided by 2 if the correct value is not set. For example,
on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
1.05 GHz.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| #
c851a245 |
| 24-Aug-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-socfpga
Conflicts:
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_socrates_defconfig
Merged these by hand and re-ran savedefco
Merge git://git.denx.de/u-boot-socfpga
Conflicts:
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_socrates_defconfig
Merged these by hand and re-ran savedefconfig on them.
Signed-off-by: Tom Rini <trini@konsulko.com>
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| #
ca62d2e1 |
| 02-Aug-2015 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Move wrappers into platform directory
Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it p
arm: socfpga: Move wrappers into platform directory
Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.
Signed-off-by: Marek Vasut <marex@denx.de>
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