Searched hist:"8 c597bca4fd328fbc891b09c56ffbda191e02782" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | dw_hdmi_qp.h | 8c597bca4fd328fbc891b09c56ffbda191e02782 Mon Sep 05 03:14:41 UTC 2022 Algea Cao <algea.cao@rock-chips.com> video/drm: dw-hdmi-qp: Optimize HDMI enable process
1.Support phy pll clk enable/disable is separated from
phy signal output.
2.To comply with the timing requirements of the HDMI protocol,
HDMI must be enabled in tmds mode according to the following process:
disable FRL -> enable/disable scramble —> power up phy
3.Optimize flt process
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia29337d7e82dfa09cef60447911f2fd2854bc89f
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| H A D | rockchip_dw_hdmi_qp.c | 8c597bca4fd328fbc891b09c56ffbda191e02782 Mon Sep 05 03:14:41 UTC 2022 Algea Cao <algea.cao@rock-chips.com> video/drm: dw-hdmi-qp: Optimize HDMI enable process
1.Support phy pll clk enable/disable is separated from
phy signal output.
2.To comply with the timing requirements of the HDMI protocol,
HDMI must be enabled in tmds mode according to the following process:
disable FRL -> enable/disable scramble —> power up phy
3.Optimize flt process
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia29337d7e82dfa09cef60447911f2fd2854bc89f
|
| H A D | dw_hdmi_qp.c | 8c597bca4fd328fbc891b09c56ffbda191e02782 Mon Sep 05 03:14:41 UTC 2022 Algea Cao <algea.cao@rock-chips.com> video/drm: dw-hdmi-qp: Optimize HDMI enable process
1.Support phy pll clk enable/disable is separated from
phy signal output.
2.To comply with the timing requirements of the HDMI protocol,
HDMI must be enabled in tmds mode according to the following process:
disable FRL -> enable/disable scramble —> power up phy
3.Optimize flt process
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia29337d7e82dfa09cef60447911f2fd2854bc89f
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