| #
eec52208 |
| 22-Apr-2024 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Optimized hdmi ddc transfer process
1.Reading edid consecutively 16 bytes at a time to
reduce the time consumed.
2.Increase the number of retries on failure to ensure
success
video/drm: dw-hdmi-qp: Optimized hdmi ddc transfer process
1.Reading edid consecutively 16 bytes at a time to
reduce the time consumed.
2.Increase the number of retries on failure to ensure
successful transfer.
Change-Id: I918ed91c19101afb7b3ce72ecf5d45aa17a76382
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
show more ...
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| #
463abfcc |
| 25-Feb-2024 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Support rk3576
Change-Id: I43dec093c33f730a76e91ebbe31a006b979d389d
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
|
| #
200f72c9 |
| 04-Aug-2023 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: When enable-gpio is not configured filter hdmi 2.1 resolution
Change-Id: I4e8347480d3fcd47be75a936145ebdaee742a6a4
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
|
| #
8c597bca |
| 05-Sep-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Optimize HDMI enable process
1.Support phy pll clk enable/disable is separated from
phy signal output.
2.To comply with the timing requirements of the HDMI protocol,
HDMI mu
video/drm: dw-hdmi-qp: Optimize HDMI enable process
1.Support phy pll clk enable/disable is separated from
phy signal output.
2.To comply with the timing requirements of the HDMI protocol,
HDMI must be enabled in tmds mode according to the following process:
disable FRL -> enable/disable scramble —> power up phy
3.Optimize flt process
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia29337d7e82dfa09cef60447911f2fd2854bc89f
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| #
0594ce39 |
| 27-Jun-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
video/drm: support for multi connector
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Id87d4c81e60a9f69f3fbfc05ffd67a3d42cd21a4
|
| #
cd2307e7 |
| 12-Aug-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Send VSI once per frame
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I9626c80df27fc1d4899e382e478b1633bf06f574
|
| #
99bfa312 |
| 12-Jul-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Support VSI packet
1.Support 3d mode.
2.Support hdmi1.4 4K resolution VIC number.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: If5c673e861c5498a1759519b8b7b
video/drm: dw-hdmi-qp: Support VSI packet
1.Support 3d mode.
2.Support hdmi1.4 4K resolution VIC number.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: If5c673e861c5498a1759519b8b7b76d98d34370f
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| #
626a3bcc |
| 30-Jun-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Send AVI packet once per field
Increasing the sending frequency of infoframe improves
compatibility.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I5bf4b45cb
video/drm: dw-hdmi-qp: Send AVI packet once per field
Increasing the sending frequency of infoframe improves
compatibility.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I5bf4b45cbddea02fcb3aa39262ac4ad32a3397c1
show more ...
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| #
cebdc49b |
| 11-May-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Workaround for FRL mode no signal after plug
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I8be564981f25c8854c9870c8d0599ba06c88976f
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| #
0d7a8537 |
| 23-Feb-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Support rk3588 hdmi force-output mode
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I828f94b005ed6a5ca6eec1ac96c8ac55da396c6c
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| #
28671eda |
| 22-Jan-2022 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: dw-hdmi-qp: Support dw-hdmi-qp
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I63477c492a3f570f06c958f2aec3bd5c7cbdca25
|