Searched hist:"8008 babd58f60c91a88ad79df3d32f63596b433a" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a78c.h | 8008babd58f60c91a88ad79df3d32f63596b433a Tue Jul 12 15:43:52 UTC 2022 laurenw-arm <lauren.wehrmeister@arm.com> fix(errata): workaround for Cortex-A78C 2132064
Cortex-A78C erratum 2132064 is a cat B erratum that applies to revisions
r0p1 and r0p2 and is still open.
This patch implements workaround option 2 that places the data
prefetcher in the most conservative mode to greatly reduce prefetches
by writing the following bits to the value indicated:
ecltr[7:6], PF_MODE = 2'b11
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ica2561c1e257643c2482085447ef852fa62a1eb2
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a78c.S | 8008babd58f60c91a88ad79df3d32f63596b433a Tue Jul 12 15:43:52 UTC 2022 laurenw-arm <lauren.wehrmeister@arm.com> fix(errata): workaround for Cortex-A78C 2132064
Cortex-A78C erratum 2132064 is a cat B erratum that applies to revisions
r0p1 and r0p2 and is still open.
This patch implements workaround option 2 that places the data
prefetcher in the most conservative mode to greatly reduce prefetches
by writing the following bits to the value indicated:
ecltr[7:6], PF_MODE = 2'b11
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ica2561c1e257643c2482085447ef852fa62a1eb2
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 8008babd58f60c91a88ad79df3d32f63596b433a Tue Jul 12 15:43:52 UTC 2022 laurenw-arm <lauren.wehrmeister@arm.com> fix(errata): workaround for Cortex-A78C 2132064
Cortex-A78C erratum 2132064 is a cat B erratum that applies to revisions
r0p1 and r0p2 and is still open.
This patch implements workaround option 2 that places the data
prefetcher in the most conservative mode to greatly reduce prefetches
by writing the following bits to the value indicated:
ecltr[7:6], PF_MODE = 2'b11
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ica2561c1e257643c2482085447ef852fa62a1eb2
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 8008babd58f60c91a88ad79df3d32f63596b433a Tue Jul 12 15:43:52 UTC 2022 laurenw-arm <lauren.wehrmeister@arm.com> fix(errata): workaround for Cortex-A78C 2132064
Cortex-A78C erratum 2132064 is a cat B erratum that applies to revisions
r0p1 and r0p2 and is still open.
This patch implements workaround option 2 that places the data
prefetcher in the most conservative mode to greatly reduce prefetches
by writing the following bits to the value indicated:
ecltr[7:6], PF_MODE = 2'b11
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ica2561c1e257643c2482085447ef852fa62a1eb2
|