10a144dd4SBipin Ravi /* 2*ac9f4b4dSGovindraj Raja * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 30a144dd4SBipin Ravi * 40a144dd4SBipin Ravi * SPDX-License-Identifier: BSD-3-Clause 50a144dd4SBipin Ravi */ 60a144dd4SBipin Ravi 70a144dd4SBipin Ravi #ifndef CORTEX_A78C_H 80a144dd4SBipin Ravi #define CORTEX_A78C_H 90a144dd4SBipin Ravi 100a144dd4SBipin Ravi 110a144dd4SBipin Ravi #define CORTEX_A78C_MIDR U(0x410FD4B1) 120a144dd4SBipin Ravi 135f802c88SBipin Ravi /* Cortex-A76 loop count for CVE-2022-23960 mitigation */ 145f802c88SBipin Ravi #define CORTEX_A78C_BHB_LOOP_COUNT U(32) 155f802c88SBipin Ravi 160a144dd4SBipin Ravi /******************************************************************************* 174b6f0026SAkram Ahmad * CPU Auxiliary Control register 2 specific definitions. 184b6f0026SAkram Ahmad * ****************************************************************************/ 194b6f0026SAkram Ahmad #define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1 205d3c1f58SAkram Ahmad #define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 214b6f0026SAkram Ahmad #define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 224b6f0026SAkram Ahmad 234b6f0026SAkram Ahmad /******************************************************************************* 240a144dd4SBipin Ravi * CPU Extended Control register specific definitions. 250a144dd4SBipin Ravi ******************************************************************************/ 260a144dd4SBipin Ravi #define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4 27672eb21eSBipin Ravi #define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53) 280a144dd4SBipin Ravi 290a144dd4SBipin Ravi /******************************************************************************* 300a144dd4SBipin Ravi * CPU Power Control register specific definitions 310a144dd4SBipin Ravi ******************************************************************************/ 320a144dd4SBipin Ravi #define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7 330a144dd4SBipin Ravi #define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 340a144dd4SBipin Ravi 356979f47fSBipin Ravi /******************************************************************************* 3666bf3ba4SBipin Ravi * CPU Auxiliary Control register 3 specific definitions. 3766bf3ba4SBipin Ravi ******************************************************************************/ 3866bf3ba4SBipin Ravi #define CORTEX_A78C_ACTLR3_EL1 S3_0_C15_C1_2 3966bf3ba4SBipin Ravi 4066bf3ba4SBipin Ravi /******************************************************************************* 416979f47fSBipin Ravi * CPU Implementation Specific Selected Instruction registers 426979f47fSBipin Ravi ******************************************************************************/ 436979f47fSBipin Ravi #define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 446979f47fSBipin Ravi #define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1 456979f47fSBipin Ravi #define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2 466979f47fSBipin Ravi #define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3 476979f47fSBipin Ravi 4881d4094dSSona Mathew /******************************************************************************* 4981d4094dSSona Mathew * CPU Auxiliary Control register 5 specific definitions. 5081d4094dSSona Mathew ******************************************************************************/ 5181d4094dSSona Mathew #define CORTEX_A78C_ACTLR5_EL1 S3_0_C15_C9_0 5281d4094dSSona Mathew 530a144dd4SBipin Ravi #endif /* CORTEX_A78C_H */ 54