Merge "fix(cpus): remove errata setting PF_MODE to conservative" into integration

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A. The current workaround attempts to follow option 2 but
misapplies it. Specifically, it statically sets PF_MODE to
conservative, which is not the recommended approach. According to the
erratum documentation, PF_MODE should be configured in conservative
mode only when we disable data prefetcher however this is not done
in TF-A and thus the workaround is not needed in TF-A.

The static setting of PF_MODE in TF-A does not correctly address the
erratum and may introduce unnecessary performance degradation on
platforms that adopt it without fully understanding its implications.

To prevent incorrect or unintended use, the current implementation of
this erratum workaround should be removed from TF-A and not adopted by
platforms.

List of Impacted CPU's with Errata Numbers and reference to SDEN -

Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest
Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest
Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest
Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest
Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest
Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest
Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest
Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "sm/errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workarou

Merge changes from topic "sm/errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workaround for Cortex-X3 erratum 2779509

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fix(cpus): workaround for Cortex-A78C erratum 2743232

Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1

fix(cpus): workaround for Cortex-A78C erratum 2743232

Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2004089/latest

Change-Id: Ic62579c2dd69b7a8cbbeaa936f45b2cc9436439a
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 1827440
fix(cpus): workaround for Cortex-A78C erratum 1827430

fix(cpus): workaround for Cortex-A78C erratum 1827430

Cortex-A78C erratum 1827430 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1.

The workaround is to set the CPUECTLR_EL1[53

fix(cpus): workaround for Cortex-A78C erratum 1827430

Cortex-A78C erratum 1827430 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1.

The workaround is to set the CPUECTLR_EL1[53] to 1, which disables
allocation of splintered pages in the L2 TLB.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1707916/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie68771bdd3bddeff54d06b6a456dad4a7fc27426

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Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2779484
fix(cpus): workaround for Cortex-A78 erratum 2742426

fix(cpus): workaround for Cortex-A78C erratum 2779484

Cortex-A78C erratum 2779484 is a Cat B erratum that applies to
revisions r0p1 and r0p2 and is still open.

The workaround is to set the CPUACTLR

fix(cpus): workaround for Cortex-A78C erratum 2779484

Cortex-A78C erratum 2779484 is a Cat B erratum that applies to
revisions r0p1 and r0p2 and is still open.

The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this
bit might have a small impact on power and negligible impact on
performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I9a8c16a845c3ba6eb2f17a5119aa6ca09a0d27ed

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Merge "fix(cpus): workaround for Cortex-A78C erratum 2376749" into integration

fix(cpus): workaround for Cortex-A78C erratum 2376749

Cortex-A78C erratum 2376749 is a Cat B erratum that applies
to revisions r0p1 and r0p2 of the A78C and is currently open.
The workaround is to s

fix(cpus): workaround for Cortex-A78C erratum 2376749

Cortex-A78C erratum 2376749 is a Cat B erratum that applies
to revisions r0p1 and r0p2 of the A78C and is currently open.
The workaround is to set CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause
invalidations to other PE caches.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I3b29f4b7f167bf499d5d11ffef91a94861bd1383

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Merge "fix(errata): workaround for Cortex-A78C erratum 2395411" into integration

fix(errata): workaround for Cortex-A78C erratum 2395411

Cortex-A78C erratum 2395411 is a Cat B erratum that affects
revisions r0p1 and r0p2, and is currently open. The workaround
is to set CPUACTLR2

fix(errata): workaround for Cortex-A78C erratum 2395411

Cortex-A78C erratum 2395411 is a Cat B erratum that affects
revisions r0p1 and r0p2, and is currently open. The workaround
is to set CPUACTLR2_EL1[40] to 1, which will disable folding
of demand requests into older prefetches with L2 miss requests
outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4f0fb278ac20a2eb4dd7e4efd1b1246dd85e48c4

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Merge "fix(errata): workaround for Cortex A78C erratum 2242638" into integration

fix(errata): workaround for Cortex A78C erratum 2242638

Cortex A78C erratum 2242638 is a Cat B erratum which applies to
revisions r0p1, r0p2 and is still open. The workaround is to apply
a CPU imple

fix(errata): workaround for Cortex A78C erratum 2242638

Cortex A78C erratum 2242638 is a Cat B erratum which applies to
revisions r0p1, r0p2 and is still open. The workaround is to apply
a CPU implementation specific specific patch sequence.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I35d385245a04a39b87be71c1a42312f75e1152e5

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Merge "fix(errata): workaround for Cortex-A78C 2132064" into integration

fix(errata): workaround for Cortex-A78C 2132064

Cortex-A78C erratum 2132064 is a cat B erratum that applies to revisions
r0p1 and r0p2 and is still open.

This patch implements workaround option 2 t

fix(errata): workaround for Cortex-A78C 2132064

Cortex-A78C erratum 2132064 is a cat B erratum that applies to revisions
r0p1 and r0p2 and is still open.

This patch implements workaround option 2 that places the data
prefetcher in the most conservative mode to greatly reduce prefetches
by writing the following bits to the value indicated:
ecltr[7:6], PF_MODE = 2'b11

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ica2561c1e257643c2482085447ef852fa62a1eb2

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Merge "fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C" into integration

fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C

Implements the loop workaround for Cortex-A76AE, Cortex-A78AE and
Cortex-A78C.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Sig

fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C

Implements the loop workaround for Cortex-A76AE, Cortex-A78AE and
Cortex-A78C.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I5c838f5b9d595ed3c461a7452bd465bd54acc548

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Merge "Add Cortex_A78C CPU lib" into integration

Add Cortex_A78C CPU lib

Add basic support for Cortex_A78C CPU.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56