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| /rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/ |
| H A D | pm_api_ioctl.h | 7c0b17e34b28decfab4f7de361fbbfd8b18b3e33 Tue Sep 04 11:33:25 UTC 2018 Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> zynqmp: pm_service: Add support for resetting ULPI transceiver
To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is being driven by BOOT MODE PIN 1. The BOOT MODE PIN's
are controlled by BOOT_PIN_CTRL register present in CRL_APB
address region. Since CRL_APB can be resticted to secure access,
this pin should be controlled by ATF.
This patch adds the support for the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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| H A D | pm_api_ioctl.c | 7c0b17e34b28decfab4f7de361fbbfd8b18b3e33 Tue Sep 04 11:33:25 UTC 2018 Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> zynqmp: pm_service: Add support for resetting ULPI transceiver
To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is being driven by BOOT MODE PIN 1. The BOOT MODE PIN's
are controlled by BOOT_PIN_CTRL register present in CRL_APB
address region. Since CRL_APB can be resticted to secure access,
this pin should be controlled by ATF.
This patch adds the support for the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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