Searched hist:"7 b8c75546bd14849589723e26aba6efb1782cc4b" (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/arch/arm/plat-stm32mp2/ |
| H A D | stm32_sysconf.h | 7b8c75546bd14849589723e26aba6efb1782cc4b Tue Jun 03 13:13:02 UTC 2025 Gabriel Fernandez <gabriel.fernandez@foss.st.com> clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz
When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
because the clkext2f frequency of 400MHz is not supported.
This patch also rename the function stm32mp2_a35_ss_on_hsi to
stm32mp2_a35_ss_on_bypass to be aligned with reference manual.
Fixes: 28c10f9efa6a ("clk: stm32mp25: Introduce STM32MP25 clocks platform")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
|
| /optee_os/core/drivers/clk/ |
| H A D | clk-stm32mp25.c | 7b8c75546bd14849589723e26aba6efb1782cc4b Tue Jun 03 13:13:02 UTC 2025 Gabriel Fernandez <gabriel.fernandez@foss.st.com> clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz
When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
because the clkext2f frequency of 400MHz is not supported.
This patch also rename the function stm32mp2_a35_ss_on_hsi to
stm32mp2_a35_ss_on_bypass to be aligned with reference manual.
Fixes: 28c10f9efa6a ("clk: stm32mp25: Introduce STM32MP25 clocks platform")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
|