Searched hist:"7 ac7dadb551ee602299aef91043dc4adbd234a3e" (Results 1 – 8 of 8) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/common/drivers/ccu/ |
| H A D | ncore_ccu.h | 7ac7dadb551ee602299aef91043dc4adbd234a3e Mon Oct 21 17:00:45 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| H A D | ncore_ccu.c | 7ac7dadb551ee602299aef91043dc4adbd234a3e Mon Oct 21 17:00:45 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/common/include/ |
| H A D | socfpga_private.h | 7ac7dadb551ee602299aef91043dc4adbd234a3e Mon Oct 21 17:00:45 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/common/aarch64/ |
| H A D | plat_helpers.S | 7ac7dadb551ee602299aef91043dc4adbd234a3e Mon Oct 21 17:00:45 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/common/ |
| H A D | socfpga_psci.c | 7ac7dadb551ee602299aef91043dc4adbd234a3e Mon Oct 21 17:00:45 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex5/include/ |
| H A D | socfpga_plat_def.h | 7ac7dadb551ee602299aef91043dc4adbd234a3e Mon Oct 21 17:00:45 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex/include/ |
| H A D | socfpga_plat_def.h | 7ac7dadb551ee602299aef91043dc4adbd234a3e Mon Oct 21 17:00:45 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/stratix10/ |
| H A D | platform.mk | 7ac7dadb551ee602299aef91043dc4adbd234a3e Mon Oct 21 17:00:45 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|