Searched hist:"51 f366ac85c22bc2a3a729192acba7cb7a2cbb13" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/stratix10/include/ |
| H A D | s10_memory_controller.h | 51f366ac85c22bc2a3a729192acba7cb7a2cbb13 Wed Feb 13 06:39:31 UTC 2019 Loh Tien Hock <tien.hock.loh@intel.com> plat: intel: Fix faulty DDR calibration value
A DDR calibration value is missing write mask, causing ECC DDR calibration
to fail. This patch addresses the issue. ECC should also be scrubbed before
MMU initializes, thus the scrubbing is moved to ddr intialization phase.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/stratix10/soc/ |
| H A D | s10_memory_controller.c | 51f366ac85c22bc2a3a729192acba7cb7a2cbb13 Wed Feb 13 06:39:31 UTC 2019 Loh Tien Hock <tien.hock.loh@intel.com> plat: intel: Fix faulty DDR calibration value
A DDR calibration value is missing write mask, causing ECC DDR calibration
to fail. This patch addresses the issue. ECC should also be scrubbed before
MMU initializes, thus the scrubbing is moved to ddr intialization phase.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/stratix10/ |
| H A D | bl2_plat_setup.c | 51f366ac85c22bc2a3a729192acba7cb7a2cbb13 Wed Feb 13 06:39:31 UTC 2019 Loh Tien Hock <tien.hock.loh@intel.com> plat: intel: Fix faulty DDR calibration value
A DDR calibration value is missing write mask, causing ECC DDR calibration
to fail. This patch addresses the issue. ECC should also be scrubbed before
MMU initializes, thus the scrubbing is moved to ddr intialization phase.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
|