Searched hist:"46 a08aab4c56ad9e3f57b127a02fead1e6b8cf38" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/xilinx/versal_net/include/ |
| H A D | platform_def.h | 46a08aab4c56ad9e3f57b127a02fead1e6b8cf38 Mon Jul 10 05:13:29 UTC 2023 Amit Nagal <amit.nagal@amd.com> feat(versal-net): ddr address reservation in dtb at runtime
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
|
| /rk3399_ARM-atf/plat/xilinx/versal_net/ |
| H A D | platform.mk | 46a08aab4c56ad9e3f57b127a02fead1e6b8cf38 Mon Jul 10 05:13:29 UTC 2023 Amit Nagal <amit.nagal@amd.com> feat(versal-net): ddr address reservation in dtb at runtime
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
|
| H A D | bl31_versal_net_setup.c | 46a08aab4c56ad9e3f57b127a02fead1e6b8cf38 Mon Jul 10 05:13:29 UTC 2023 Amit Nagal <amit.nagal@amd.com> feat(versal-net): ddr address reservation in dtb at runtime
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
|