Searched hist:"3 b4456ec391877a950dd5e98ee20df6560f0e1af" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/include/configs/ |
| H A D | P4080DS.h | 3b4456ec391877a950dd5e98ee20df6560f0e1af Fri Jan 07 06:06:47 UTC 2011 Roy Zang <tie-fei.zang@freescale.com> fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.
Clear these bits out when we read HOSTCAPBLT.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | cmd_errata.c | 3b4456ec391877a950dd5e98ee20df6560f0e1af Fri Jan 07 06:06:47 UTC 2011 Roy Zang <tie-fei.zang@freescale.com> fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.
Clear these bits out when we read HOSTCAPBLT.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| /rk3399_rockchip-uboot/drivers/mmc/ |
| H A D | fsl_esdhc.c | 3b4456ec391877a950dd5e98ee20df6560f0e1af Fri Jan 07 06:06:47 UTC 2011 Roy Zang <tie-fei.zang@freescale.com> fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.
Clear these bits out when we read HOSTCAPBLT.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|