Searched hist:"2454316 c2ae4411d0071d88c3db3c95598f12498" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_x3.h | 2454316c2ae4411d0071d88c3db3c95598f12498 Tue Oct 03 22:09:09 UTC 2023 Sona Mathew <sonarebecca.mathew@arm.com> fix(cpus): workaround for Cortex-X3 erratum 2070301
Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001 to the PF_MODE bits
in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher
in the most conservative mode instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_x3.S | 2454316c2ae4411d0071d88c3db3c95598f12498 Tue Oct 03 22:09:09 UTC 2023 Sona Mathew <sonarebecca.mathew@arm.com> fix(cpus): workaround for Cortex-X3 erratum 2070301
Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001 to the PF_MODE bits
in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher
in the most conservative mode instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
|
| /rk3399_ARM-atf/services/std_svc/errata_abi/ |
| H A D | errata_abi_main.c | 2454316c2ae4411d0071d88c3db3c95598f12498 Tue Oct 03 22:09:09 UTC 2023 Sona Mathew <sonarebecca.mathew@arm.com> fix(cpus): workaround for Cortex-X3 erratum 2070301
Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001 to the PF_MODE bits
in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher
in the most conservative mode instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 2454316c2ae4411d0071d88c3db3c95598f12498 Tue Oct 03 22:09:09 UTC 2023 Sona Mathew <sonarebecca.mathew@arm.com> fix(cpus): workaround for Cortex-X3 erratum 2070301
Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001 to the PF_MODE bits
in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher
in the most conservative mode instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 2454316c2ae4411d0071d88c3db3c95598f12498 Tue Oct 03 22:09:09 UTC 2023 Sona Mathew <sonarebecca.mathew@arm.com> fix(cpus): workaround for Cortex-X3 erratum 2070301
Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001 to the PF_MODE bits
in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher
in the most conservative mode instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
|