Searched hist:"18 f2efd67d881fe0a9a535ce9e801e60d746e024" (Results 1 – 7 of 7) sorted by relevance
| /rk3399_ARM-atf/bl1/aarch32/ |
| H A D | bl1_entrypoint.S | 18f2efd67d881fe0a9a535ce9e801e60d746e024 Thu Apr 13 21:38:29 UTC 2017 David Cunado <david.cunado@arm.com> Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.
The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.
This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.
This patch also corrects the following typos:
"NASCR definitions" -> "NSACR definitions"
Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>
|
| /rk3399_ARM-atf/include/common/ |
| H A D | ep_info.h | 18f2efd67d881fe0a9a535ce9e801e60d746e024 Thu Apr 13 21:38:29 UTC 2017 David Cunado <david.cunado@arm.com> Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.
The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.
This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.
This patch also corrects the following typos:
"NASCR definitions" -> "NSACR definitions"
Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>
|
| /rk3399_ARM-atf/bl32/sp_min/aarch32/ |
| H A D | entrypoint.S | 18f2efd67d881fe0a9a535ce9e801e60d746e024 Thu Apr 13 21:38:29 UTC 2017 David Cunado <david.cunado@arm.com> Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.
The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.
This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.
This patch also corrects the following typos:
"NASCR definitions" -> "NSACR definitions"
Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>
|
| /rk3399_ARM-atf/lib/el3_runtime/aarch32/ |
| H A D | context_mgmt.c | 18f2efd67d881fe0a9a535ce9e801e60d746e024 Thu Apr 13 21:38:29 UTC 2017 David Cunado <david.cunado@arm.com> Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.
The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.
This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.
This patch also corrects the following typos:
"NASCR definitions" -> "NSACR definitions"
Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>
|
| /rk3399_ARM-atf/bl1/aarch64/ |
| H A D | bl1_entrypoint.S | 18f2efd67d881fe0a9a535ce9e801e60d746e024 Thu Apr 13 21:38:29 UTC 2017 David Cunado <david.cunado@arm.com> Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.
The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.
This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.
This patch also corrects the following typos:
"NASCR definitions" -> "NSACR definitions"
Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>
|
| /rk3399_ARM-atf/bl31/aarch64/ |
| H A D | bl31_entrypoint.S | 18f2efd67d881fe0a9a535ce9e801e60d746e024 Thu Apr 13 21:38:29 UTC 2017 David Cunado <david.cunado@arm.com> Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.
The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.
This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.
This patch also corrects the following typos:
"NASCR definitions" -> "NSACR definitions"
Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>
|
| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context_mgmt.c | 18f2efd67d881fe0a9a535ce9e801e60d746e024 Thu Apr 13 21:38:29 UTC 2017 David Cunado <david.cunado@arm.com> Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.
The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.
This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.
This patch also corrects the following typos:
"NASCR definitions" -> "NSACR definitions"
Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>
|