Searched hist:"0 de0139e0300eb7102032e47a3cf8eb680f98a6f" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3568.h | 0de0139e0300eb7102032e47a3cf8eb680f98a6f Fri Aug 04 09:33:59 UTC 2023 Jonas Karlman <jonas@kwiboo.se> UPSTREAM: clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Change-Id: Icc9fda366d0428b2b425a74c7ea2c5a5c1489d2f
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3568.c | 0de0139e0300eb7102032e47a3cf8eb680f98a6f Fri Aug 04 09:33:59 UTC 2023 Jonas Karlman <jonas@kwiboo.se> UPSTREAM: clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Change-Id: Icc9fda366d0428b2b425a74c7ea2c5a5c1489d2f
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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