| /rk3399_ARM-atf/plat/xilinx/common/include/ |
| H A D | pm_common.h | 03fa6f42502a3b6b318a9a73a228a6c751329a8f Mon Jun 24 08:47:39 UTC 2024 Jay Buddhabhatti <jay.buddhabhatti@amd.com> fix(xilinx): fix logic to read ipi response
Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.
So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071
|
| /rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/ |
| H A D | zynqmp_pm_svc_main.c | 03fa6f42502a3b6b318a9a73a228a6c751329a8f Mon Jun 24 08:47:39 UTC 2024 Jay Buddhabhatti <jay.buddhabhatti@amd.com> fix(xilinx): fix logic to read ipi response
Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.
So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071
|
| H A D | zynqmp_pm_api_sys.c | 03fa6f42502a3b6b318a9a73a228a6c751329a8f Mon Jun 24 08:47:39 UTC 2024 Jay Buddhabhatti <jay.buddhabhatti@amd.com> fix(xilinx): fix logic to read ipi response
Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.
So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071
|
| /rk3399_ARM-atf/plat/xilinx/versal_net/ |
| H A D | plat_psci_pm.c | 03fa6f42502a3b6b318a9a73a228a6c751329a8f Mon Jun 24 08:47:39 UTC 2024 Jay Buddhabhatti <jay.buddhabhatti@amd.com> fix(xilinx): fix logic to read ipi response
Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.
So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071
|
| /rk3399_ARM-atf/plat/xilinx/common/pm_service/ |
| H A D | pm_api_sys.c | 03fa6f42502a3b6b318a9a73a228a6c751329a8f Mon Jun 24 08:47:39 UTC 2024 Jay Buddhabhatti <jay.buddhabhatti@amd.com> fix(xilinx): fix logic to read ipi response
Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.
So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071
|
| H A D | pm_ipi.c | 03fa6f42502a3b6b318a9a73a228a6c751329a8f Mon Jun 24 08:47:39 UTC 2024 Jay Buddhabhatti <jay.buddhabhatti@amd.com> fix(xilinx): fix logic to read ipi response
Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.
So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071
|
| H A D | pm_svc_main.c | 03fa6f42502a3b6b318a9a73a228a6c751329a8f Mon Jun 24 08:47:39 UTC 2024 Jay Buddhabhatti <jay.buddhabhatti@amd.com> fix(xilinx): fix logic to read ipi response
Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.
So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071
|
| /rk3399_ARM-atf/plat/xilinx/versal/ |
| H A D | plat_psci.c | 03fa6f42502a3b6b318a9a73a228a6c751329a8f Mon Jun 24 08:47:39 UTC 2024 Jay Buddhabhatti <jay.buddhabhatti@amd.com> fix(xilinx): fix logic to read ipi response
Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.
So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071
|