Merge changes from topic "xlnx_enhancement_on_secure_and_non_secure_flag" into integration

* changes:
feat(xilinx): use common SECURE/NON_SECURE macro
fix(xilinx): incorrect usage of SECURE_FLAG

Merge changes from topic "xlnx_enhancement_on_secure_and_non_secure_flag" into integration

* changes:
feat(xilinx): use common SECURE/NON_SECURE macro
fix(xilinx): incorrect usage of SECURE_FLAG for psci

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feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE acr

feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE across all AMD-Xilinx platforms.

Change-Id: I95465e29ac8a9370da135c2113203c3206ecfec0
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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Merge changes from topic "xlnx_versal_misra_fixes_series_3" into integration

* changes:
fix(xilinx): resolve misra rule 16.3 violations
fix(xilinx): resolve misra rule 2.5 violations
fix(xilin

Merge changes from topic "xlnx_versal_misra_fixes_series_3" into integration

* changes:
fix(xilinx): resolve misra rule 16.3 violations
fix(xilinx): resolve misra rule 2.5 violations
fix(xilinx): resolve misra rule 4.6 violations
fix(xilinx): resolve misra rule 12.2 violations
fix(xilinx): resolve misra rule 10.1 violations
fix(xilinx): resolve misra rule 8.13 violations
fix(xilinx): resolve misra rule 4.5 violations
fix(xilinx): resolve misra rule 16.4 violations

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fix(xilinx): resolve misra rule 12.2 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.12.2:
- The right hand operand of a shift operator shall lie in the range
zero to

fix(xilinx): resolve misra rule 12.2 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.12.2:
- The right hand operand of a shift operator shall lie in the range
zero to one less than the width in bits of the essential type of
the left hand operand.
- Fix:
- Type casted left operand to a larger width than shift.

Change-Id: I662ff57e52d1260e2f1a0de595f19a9143714892
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 10.1 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.1:
- Operands shall not be of an inappropriate essential type.
- Fix:
- Made ope

fix(xilinx): resolve misra rule 10.1 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.1:
- Operands shall not be of an inappropriate essential type.
- Fix:
- Made operands of the same type.

Change-Id: I30a01cc0938603defba7572e9f4dd9ebe6d74a9c
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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Merge "fix(xilinx): fix OVERRUN coverity violation" into integration

fix(xilinx): fix OVERRUN coverity violation

This change fixes below MISRA violation:
CID 441243: Memory - corruptions (OVERRUN)
Overrunning callee's array of size 7 by passing argument "7UL" in ca

fix(xilinx): fix OVERRUN coverity violation

This change fixes below MISRA violation:
CID 441243: Memory - corruptions (OVERRUN)
Overrunning callee's array of size 7 by passing argument "7UL" in call to
"pm_ipi_send_sync".

Change-Id: Ie7fd9ccad058e97eb4b36c4f0e77be8bfb3e6006
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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Merge changes from topic "xlnx_tfa_passthrough_plm_ipi_cmd" into integration

* changes:
docs(xilinx): update SMC documentation in TF-A
feat(xilinx): add feature check function for TF-A specific

Merge changes from topic "xlnx_tfa_passthrough_plm_ipi_cmd" into integration

* changes:
docs(xilinx): update SMC documentation in TF-A
feat(xilinx): add feature check function for TF-A specific APIs
feat(xilinx): update SiP SVC version number
feat(xilinx): update TF-A to passthrough all PLM commands
fix(xilinx): fix logic to read ipi response

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fix(xilinx): fix logic to read ipi response

Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret stat

fix(xilinx): fix logic to read ipi response

Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.

So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071

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Merge "chore(xilinx): follow kernel doc format for functional documentation" into integration

chore(xilinx): follow kernel doc format for functional documentation

For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for th

chore(xilinx): follow kernel doc format for functional documentation

For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for the functional
documentation to make sure AMD-xilinx documentation is align with
actual code.

For example use kernel-doc from linux to call:
<linux>/scripts/kernel-doc -man -v 1 >/dev/null file...

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Idcc9def408b6c8da35b36f67ef82fc00890e998c

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Merge "style(xilinx): replace ARM by Arm in copyrights" into integration

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.

Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "feat(versal): update macro name to generic and move to common place" into integration

feat(versal): update macro name to generic and move to common place

Update TZ_VERSION macro name to generic macro name and move to
common header file so that it can be used for keystoneb.

Signed-of

feat(versal): update macro name to generic and move to common place

Update TZ_VERSION macro name to generic macro name and move to
common header file so that it can be used for keystoneb.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Acked-by: Tanmay Shah <tanmay.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic3819eea78b6c7b51ffaa13081026dd191b76125

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Merge changes from topic "xlnx_zynqmp_misra_fix1" into integration

* changes:
fix(zynqmp): resolve the misra 8.6 warnings
fix(zynqmp): resolve the misra 4.6 warnings

fix(zynqmp): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by:

fix(zynqmp): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I9fb686e7aa2b85af6dfcb7bb5f87eddf469fb85c

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Merge changes I3c25c715,I6d30b081 into integration

* changes:
plat: xilinx: versal: Add the IPI CRC checksum macro support
plat: xilinx: common: Rename the IPI CRC checksum macro

plat: xilinx: common: Rename the IPI CRC checksum macro

Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and
move the related defines to the common include.

Signed-off-by: Venkatesh Yadav Abb

plat: xilinx: common: Rename the IPI CRC checksum macro

Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and
move the related defines to the common include.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I6d30b081ac607572a0b23e10ca8031bc90489e58

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Merge pull request #1744 from jollysxilinx/integration

plat: xilinx: code restructure

xilinx: Move IPI functions to common file

pm_service ipi functions can be used by other xilinx
platforms. So move it to common directory. Also change
node_id member type in pm_proc structure so it c

xilinx: Move IPI functions to common file

pm_service ipi functions can be used by other xilinx
platforms. So move it to common directory. Also change
node_id member type in pm_proc structure so it can be
used for versal where device IDs are used instead of
node IDs.

To accommodate this change header files are re-organized.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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