Searched hist:"031 acdbae89515371f794d01df819b490ff7ca9c" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | fsl_lsch2_serdes.c | 031acdbae89515371f794d01df819b490ff7ca9c Fri Dec 09 08:09:00 UTC 2016 Hou Zhiqiang <Zhiqiang.Hou@nxp.com> armv8/fsl_lsch2: Add chip power supply voltage setup
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.
Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| H A D | soc.c | 031acdbae89515371f794d01df819b490ff7ca9c Fri Dec 09 08:09:00 UTC 2016 Hou Zhiqiang <Zhiqiang.Hou@nxp.com> armv8/fsl_lsch2: Add chip power supply voltage setup
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.
Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | fsl_serdes.h | 031acdbae89515371f794d01df819b490ff7ca9c Fri Dec 09 08:09:00 UTC 2016 Hou Zhiqiang <Zhiqiang.Hou@nxp.com> armv8/fsl_lsch2: Add chip power supply voltage setup
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.
Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| H A D | soc.h | 031acdbae89515371f794d01df819b490ff7ca9c Fri Dec 09 08:09:00 UTC 2016 Hou Zhiqiang <Zhiqiang.Hou@nxp.com> armv8/fsl_lsch2: Add chip power supply voltage setup
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.
Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| /rk3399_rockchip-uboot/include/ |
| H A D | fsl_ddr_sdram.h | 031acdbae89515371f794d01df819b490ff7ca9c Fri Dec 09 08:09:00 UTC 2016 Hou Zhiqiang <Zhiqiang.Hou@nxp.com> armv8/fsl_lsch2: Add chip power supply voltage setup
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.
Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|