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/OK3568_Linux_fs/kernel/drivers/phy/broadcom/
H A Dphy-bcm-ns-usb3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom Northstar USB 3.0 PHY Driver
22 #include <linux/phy/phy.h>
56 struct phy *phy; member
58 int (*phy_write)(struct bcm_ns_usb3 *usb3, u16 reg, u16 value);
63 .compatible = "brcm,ns-ax-usb3-phy",
67 .compatible = "brcm,ns-bx-usb3-phy",
74 static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, in bcm_ns_usb3_mdio_phy_write() argument
77 return usb3->phy_write(usb3, reg, value); in bcm_ns_usb3_mdio_phy_write()
80 static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) in bcm_ns_usb3_phy_init_ns_bx() argument
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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H A Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
34 --------------------
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H A Dqcom,qmp-usb3-dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7180-qmp-usb3-phy
18 - qcom,sdm845-qmp-usb3-dp-phy
19 - qcom,sdm845-qmp-usb3-phy
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H A Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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H A Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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H A Dqcom,qmp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QMP phy controller supports physical layer functionality for a number of
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
22 - qcom,msm8996-qmp-pcie-phy
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H A Dbcm-ns-usb3-phy.txt1 Driver for Broadcom Northstar USB 3.0 PHY
5 - compatible: one of: "brcm,ns-ax-usb3-phy", "brcm,ns-bx-usb3-phy".
6 - reg: address of MDIO bus device
7 - usb3-dmp-syscon: phandle to syscon with DMP (Device Management Plugin)
9 - #phy-cells: must be 0
11 Initialization of USB 3.0 PHY depends on Northstar version. There are currently
21 #size-cells = <1>;
22 #address-cells = <0>;
24 usb3-phy@10 {
25 compatible = "brcm,ns-ax-usb3-phy";
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H A Damlogic,meson-g12a-usb3-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <narmstrong@baylibre.com>
16 - amlogic,meson-g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
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H A Dallwinner,sun50i-h6-usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Allwinner H6 USB3 PHY
11 - Ondrej Jirman <megous@megous.com>
16 - allwinner,sun50i-h6-usb3-phy
27 "#phy-cells":
31 - compatible
32 - reg
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H A Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
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H A Dti-phy.txt1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
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/OK3568_Linux_fs/kernel/drivers/phy/tegra/
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/phy/phy.h>
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
149 /* USB 2.0 UTMI PHY support */
159 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
161 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
162 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
163 usb2->base.index = index; in tegra186_usb2_lane_probe()
164 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
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H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/phy/phy.h>
13 #include <linux/phy/tegra/xusb.h>
24 static struct phy *tegra_xusb_pad_of_xlate(struct device *dev, in tegra_xusb_pad_of_xlate()
28 struct phy *phy = NULL; in tegra_xusb_pad_of_xlate() local
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra124-xusb.txt4 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
17 - "hcd"
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H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare USB3 Controller
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
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H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
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H A Drockchip-inno,dwc3.txt1 Rockchip SuperSpeed DWC3 USB SoC controller with INNO USB3 PHY inside
4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3328-dwc3"
6 * "rockchip,rk322xh-dwc3"
7 - clocks : a list of phandle + clock-specifier pairs for the
8 clocks listed in clock-names.
9 - clock-names : Should contain the following:
19 Phy documentation is provided in the following places:
20 Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.txt
24 u3phy: usb3-phy@ff470000 {
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/OK3568_Linux_fs/kernel/drivers/phy/socionext/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY drivers for Socionext platforms.
7 tristate "UniPhier USB2 PHY driver"
13 Enable this to support USB PHY implemented on USB2 controller
15 with USB 2.0 PHY that is part of the UniPhier SoC.
16 In case of Pro4, it is necessary to specify this USB2 PHY instead
17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
25 Enable this to support USB PHY implemented in USB3 controller
26 on UniPhier SoCs. This controller supports USB3.0 and lower speed.
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H A Dphy-uniphier-usb3ss.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-usb3ss.c - SS-PHY driver for Socionext UniPhier USB3 controller
4 * Copyright 2015-2018 Socionext Inc.
19 #include <linux/phy/phy.h>
73 writel(data, priv->base + SSPHY_TESTI); in uniphier_u3ssphy_testio_write()
74 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
75 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
82 u8 field_mask = GENMASK(p->field.msb, p->field.lsb); in uniphier_u3ssphy_set_param()
87 val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no); in uniphier_u3ssphy_set_param()
89 val = readl(priv->base + SSPHY_TESTO) & TESTO_DAT_MASK; in uniphier_u3ssphy_set_param()
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/OK3568_Linux_fs/kernel/drivers/usb/gadget/udc/
H A Drenesas_usb3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas USB3.0 Peripheral driver (USB gadget)
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
10 #include <linux/dma-mapping.h>
12 #include <linux/extcon-provider.h>
17 #include <linux/phy/phy.h>
35 #define USB3_DMA_CH0_CON(n) (0x030 + ((n) - 1) * 0x10) /* n = 1 to 4 */
36 #define USB3_DMA_CH0_PRD_ADR(n) (0x034 + ((n) - 1) * 0x10) /* n = 1 to 4 */
75 #define AXI_INT_PRDEN_CLR_STA_SHIFT(n) (16 + (n) - 1)
76 #define AXI_INT_PRDERR_STA_SHIFT(n) (0 + (n) - 1)
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/nvidia/
H A Dtegra194-p2972-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra194-p2888.dtsi"
11 compatible = "nvidia,p2972-0000", "nvidia,tegra194";
17 dma-controller@2930000 {
21 interrupt-controller@2a40000 {
32 vcc-supply = <&vdd_1v8ls>;
33 address-width = <8>;
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/OK3568_Linux_fs/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
36 /*-----------------------------------------------------------*/
114 for (; timeout > 0; timeout--) { in comphy_poll_reg()
256 * 1. Select 40-bit data width width in comphy_sata_power_up()
262 * 2. Select reference clock and PHY mode (SATA) in comphy_sata_power_up()
287 * 5. Set vendor-specific configuration (??) in comphy_sata_power_up()
327 * 2. Set counter for 100us pulse in USB3 Host and Device in comphy_usb3_power_up()
335 /* set PRD_TXDEEMPH (3.5db de-emph) */ in comphy_usb3_power_up()
336 reg_set16((void __iomem *)LANE_CFG0_ADDR(USB3), 0x1, 0xFF); in comphy_usb3_power_up()
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/OK3568_Linux_fs/kernel/drivers/phy/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Mediatek devices
6 tristate "MediaTek T-PHY Driver"
11 Say 'Y' here to add support for MediaTek T-PHY driver,
12 it supports multiple usb2.0, usb3.0 ports, PCIe and
13 SATA, and meanwhile supports two version T-PHY which have
14 different banks layout, the T-PHY with shared banks between
15 multi-ports is first version, otherwise is second version,
19 tristate "MediaTek UFS M-PHY driver"
24 Support for UFS M-PHY on MediaTek chipsets.
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/OK3568_Linux_fs/kernel/drivers/usb/dwc3/
H A Ddwc3-keystone.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-keystone.c - Keystone Specific Glue layer
5 * Copyright (C) 2010-2013 Texas Instruments Incorporated - https://www.ti.com
7 * Author: WingMan Kwok <w-kwok2@ti.com>
14 #include <linux/dma-mapping.h>
17 #include <linux/phy/phy.h>
38 struct phy *usb3_phy;
55 val = kdwc3_readl(kdwc->usbss, USBSS_IRQENABLE_SET_0); in kdwc3_enable_irqs()
57 kdwc3_writel(kdwc->usbss, USBSS_IRQENABLE_SET_0, val); in kdwc3_enable_irqs()
64 val = kdwc3_readl(kdwc->usbss, USBSS_IRQENABLE_SET_0); in kdwc3_disable_irqs()
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