1Rockchip SuperSpeed DWC3 USB SoC controller with INNO USB3 PHY inside 2 3Required properties: 4- compatible : should be one of the listed compatibles: 5 * "rockchip,rk3328-dwc3" 6 * "rockchip,rk322xh-dwc3" 7- clocks : a list of phandle + clock-specifier pairs for the 8 clocks listed in clock-names. 9- clock-names : Should contain the following: 10 * "ref_clk" for controller reference clk, have to be 24 MHz 11 * "suspend_clk" for controller suspend clk, have to be 24 MHz or 32 KHz 12 * "bus_clk" for master/Core clock, have to be >= 62.5 MHz for SS 13 operation and >= 30MHz for HS operation. 14 15Required child node: 16A child node must exist to represent the core DWC3 IP block. The name of 17the node is not important. The content of the node is defined in dwc3.txt. 18 19Phy documentation is provided in the following places: 20Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.txt 21 22Example device nodes: 23 24 u3phy: usb3-phy@ff470000 { 25 compatible = "rockchip,rk3328-u3phy"; 26 reg = <0x0 0xff470000 0x0 0x0>; 27 ... 28 29 u3phy_utmi: utmi@ff470000 { 30 reg = <0x0 0xff470000 0x0 0x8000>; 31 #phy-cells = <0>; 32 }; 33 34 u3phy_pipe: pipe@ff478000 { 35 reg = <0x0 0xff478000 0x0 0x8000>; 36 #phy-cells = <0>; 37 }; 38 }; 39 40 usbdrd3: usb@ff600000 { 41 compatible = "rockchip,rk3328-dwc3"; 42 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 43 <&cru ACLK_USB3OTG>; 44 clock-names = "ref_clk", "suspend_clk", 45 "bus_clk"; 46 #address-cells = <2>; 47 #size-cells = <2>; 48 ranges; 49 50 usbdrd_dwc3: dwc3@ff600000 { 51 compatible = "snps,dwc3"; 52 reg = <0x0 0xff600000 0x0 0x100000>; 53 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 54 dr_mode = "host"; 55 phys = <&u3phy_utmi>, <&u3phy_pipe>; 56 phy-names = "usb2-phy", "usb3-phy"; 57 phy_type = "utmi_wide"; 58 }; 59 }; 60