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/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_hdmitx.h30 #define NOT_RST_ANALOG(x) UPDATE(x, 6, 6)
32 #define NOT_RST_DIGITAL(x) UPDATE(x, 5, 5)
34 #define REG_CLK_INV(x) UPDATE(x, 4, 4)
36 #define VCLK_INV(x) UPDATE(x, 3, 3)
38 #define REG_CLK_SOURCE(x) UPDATE(x, 2, 2)
40 #define PWR_OFF(x) UPDATE(x, 1, 1)
42 #define INT_POL(x) UPDATE(x, 0, 0)
46 #define VIDEO_INPUT_SDR_RGB444 UPDATE(0x0, 3, 1)
47 #define VIDEO_INPUT_DDR_RGB444 UPDATE(0x5, 3, 1)
48 #define VIDEO_INPUT_DDR_YCBCR422 UPDATE(0x6, 3, 1)
[all …]
H A Drk628_dsi.h20 #define TO_CLK_DIVISION(x) UPDATE(x, 15, 8)
21 #define TX_ESC_CLK_DIVISION(x) UPDATE(x, 7, 0)
23 #define DPI_VID(x) UPDATE(x, 1, 0)
26 #define DPI_COLOR_CODING(x) UPDATE(x, 3, 0)
34 #define OUTVACT_LPCMD_TIME(x) UPDATE(x, 23, 16)
35 #define INVACT_LPCMD_TIME(x) UPDATE(x, 7, 0)
44 #define CMD_VIDEO_MODE(x) UPDATE(x, 0, 0)
55 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0)
57 #define VID_PKT_SIZE(x) UPDATE(x, 13, 0)
61 #define VID_HSA_TIME(x) UPDATE(x, 11, 0)
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H A Drk628_combtxphy.h16 #define SW_TX_IDLE(x) UPDATE(x, 29, 20)
18 #define SW_TX_PD(x) UPDATE(x, 17, 8)
20 #define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5)
21 #define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5)
22 #define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5)
23 #define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5)
39 #define SW_RATE(x) UPDATE(x, 26, 24)
40 #define SW_REF_DIV(x) UPDATE(x, 20, 16)
41 #define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10)
42 #define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0)
[all …]
H A Drk628_hdmirx.h22 #define HOT_PLUG_DETECT(x) UPDATE(x, 0, 0)
37 #define SEL_PIXCLKSRC(x) UPDATE(x, 19, 18)
50 #define PREAMBLE_CNT_LIMIT(x) UPDATE(x, 31, 27)
52 #define OESSCTL3_THR(x) UPDATE(x, 20, 19)
54 #define SPIKE_FILTER_EN(x) UPDATE(x, 18, 18)
56 #define DVI_MODE_HYST(x) UPDATE(x, 17, 13)
58 #define HDMI_MODE_HYST(x) UPDATE(x, 12, 8)
60 #define HDMI_MODE(x) UPDATE(x, 7, 6)
62 #define GB_DET(x) UPDATE(x, 5, 4)
64 #define EESS_OESS(x) UPDATE(x, 3, 2)
[all …]
H A Drk628_gvi.h46 #define SYS_CTRL0_LANE_NUM(x) UPDATE(x, 7, 4)
48 #define SYS_CTRL0_BYTE_MODE(x) UPDATE(x, 9, 8)
50 #define SYS_CTRL0_SECTION_NUM(x) UPDATE(x, 11, 10)
60 #define SYS_CTRL0_GVI_GN_EN(x) UPDATE(x, 19, 16)
75 #define SYS_CTRL1_COLOR_DEPTH(x) UPDATE(x, 3, 0)
89 #define SYS_CTRL2_AFIFO_READ_THOLD(x) UPDATE(x, 7, 0)
91 #define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD(x) UPDATE(x, 23, 16)
93 #define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD(x) UPDATE(x, 31, 24)
97 #define SYS_CTRL3_LANE0_SEL(x) UPDATE(x, 2, 0)
99 #define SYS_CTRL3_LANE1_SEL(x) UPDATE(x, 6, 4)
[all …]
H A Drk628.h24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
30 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26)
32 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25)
34 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22)
36 #define SW_EDID_MODE(x) UPDATE(x, 21, 21)
38 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10)
42 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8)
44 #define SW_OUTPUT_MODE(x) UPDATE(x, 5, 3)
47 #define SW_OUTPUT_RGB_MODE(x) UPDATE(x, 7, 6)
49 #define SW_HDMITX_EN(x) UPDATE(x, 5, 5)
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/rk3399_rockchip-uboot/arch/x86/cpu/intel_common/
H A Dmicrocode.c5 * Microcode update for Intel PIII and later CPUs
26 * whether the update is applicable or not. We also use the same structure
42 struct microcode_update *update) in microcode_decode_node() argument
44 update->data = fdt_getprop(blob, node, "data", &update->size); in microcode_decode_node()
45 if (!update->data) in microcode_decode_node()
47 update->data += UCODE_HEADER_LEN; in microcode_decode_node()
48 update->size -= UCODE_HEADER_LEN; in microcode_decode_node()
50 update->header_version = fdtdec_get_int(blob, node, in microcode_decode_node()
52 update->update_revision = fdtdec_get_int(blob, node, in microcode_decode_node()
53 "intel,update-revision", 0); in microcode_decode_node()
[all …]
/rk3399_rockchip-uboot/doc/
H A DREADME.update1 Automatic software update from a TFTP server
10 boot. The update file should be a FIT file, and can contain one or more
11 updates. Each update in the update file has an address in NOR Flash where it
13 TFTP transfer is successful, the hash of each update is verified, and if the
14 verification is positive, the update is stored in Flash.
16 The auto-update feature is enabled by the CONFIG_UPDATE_TFTP macro:
21 Note that when enabling auto-update, Flash support must be turned on. Also,
27 The auto-update feature uses the following configuration knobs:
31 Normally, TFTP transfer of the update file is done to the address specified
48 Since the update file is in FIT format, it is created from an *.its file using
[all …]
H A DREADME.dfutftp15 * Update TFTP (CONFIG_UPDATE_TFTP) only supports writing
41 for USB based DFU (CONFIG_DFU_*) and DFU TFTP update
42 (CONFIG_DFU_TFTP) described in ./doc/README.update.
50 the update.c code is not enabled (CONFIG_UPDATE_TFTP) by any board in the
86 3. If required, to update firmware on boot, put the "dfu tftp 0 mmc 0" in the
99 To create FIT image for download one should follow the update tftp README file
100 (./doc/README.update) with one notable difference:
105 update@1 {
/rk3399_rockchip-uboot/scripts/
H A Dbuild-tftp-firmware.sh6 # The script to generate splited image and update.hdr for TFTP image upgrade.
8 # 2. Use FIT mechanism to record image pieces information in update.hdr: order, hash, signature, et…
9 # 3. The TFTP client download update.hdr and verify it (if need)
10 # 4. The TFTP client download => verify => flash image pieces accorrding to update.hdr.
35 echo " --force-update: enable force upgrade"
65 --force-update)
176 cat > update.its << EOF
197 };" >> update.its
210 };" >> update.its
220 cat >> update.its << EOF
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/rk3399_rockchip-uboot/drivers/video/rk_eink/
H A Drk_ebc_tcon.c35 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
65 #define DSP_HTOTAL(x) UPDATE(x, 27, 16)
66 #define DSP_HS_END(x) UPDATE(x, 7, 0)
67 #define DSP_HACT_END(x) UPDATE(x, 26, 16)
68 #define DSP_HACT_ST(x) UPDATE(x, 7, 0)
69 #define DSP_VTOTAL(x) UPDATE(x, 26, 16)
70 #define DSP_VS_END(x) UPDATE(x, 7, 0)
71 #define DSP_VACT_END(x) UPDATE(x, 26, 16)
72 #define DSP_VACT_ST(x) UPDATE(x, 7, 0)
73 #define DSP_HEIGHT(x) UPDATE(x, 26, 16)
[all …]
/rk3399_rockchip-uboot/lib/optee_clientApi/
H A DREADME16 2020.8 Update OP-TEE message protocol
21 This message protocol update involves some software component, including
31 | arch | before update | after update |
41 c20711e rk3036: tee: update optee version to v2.00
42 cb7d8f9 rk322x: tee with ta: update optee version to v2.11
43 4f9488e rk3128x: tee with ta: update optee version to v2.11
44 6d6473c rk312x: tee with ta: update optee version to v2.01
45 c0b025b rk3288: tee with ta: update optee version to v2.01
46 664ccee rk3228h/rk3328: bl32: update version to 2.01
47 6334115 rk3368: bl32: update version to 2.01
[all …]
/rk3399_rockchip-uboot/include/
H A Dpwm.h19 * @dev: PWM device to update
20 * @channel: PWM channel to update
31 * @dev: PWM device to update
32 * @channel: PWM channel to update
40 * @dev: PWM device to update
41 * @channel: PWM channel to update
53 * @dev: PWM device to update
54 * @channel: PWM channel to update
65 * @dev: PWM device to update
66 * @channel: PWM channel to update
[all …]
/rk3399_rockchip-uboot/drivers/mtd/ubi/
H A Dupd.c9 * Jan 2007: Alexander Schmidt, hacked per-volume update.
13 * This file contains implementation of the volume update and atomic LEB change
16 * The update operation is based on the per-volume update marker which is
17 * stored in the volume table. The update marker is set before the update
18 * starts, and removed after the update has been finished. So if the update was
19 * interrupted by an unclean re-boot or due to some other reasons, the update
21 * device next time. If the update marker is set for a volume, the volume is
22 * treated as damaged and most I/O operations are prohibited. Only a new update
25 * Note, in general it is possible to implement the update operation as a
41 * set_update_marker - set update marker.
[all …]
/rk3399_rockchip-uboot/common/
H A Dupdate.c13 #error "CONFIG_FIT and CONFIG_OF_LIBFDT are required for auto-update feature"
28 /* env variable holding the location of the update file */
65 /* set timeouts for auto-update */ in update_load()
72 /* download the update file */ in update_load()
254 printf("Auto-update from TFTP: "); in update_tftp()
256 /* get the file name of the update file */ in update_tftp()
264 printf("trying update file '%s'\n", filename); in update_tftp()
266 /* get load address of downloaded update file */ in update_tftp()
276 printf("Can't load update file, aborting auto-update\n"); in update_tftp()
284 printf("Bad FIT format of the update file, aborting " in update_tftp()
[all …]
/rk3399_rockchip-uboot/drivers/video/drm/
H A Drk618_dsi.c28 #define TO_CLK_DIVIDSION(x) UPDATE(x, 15, 8)
29 #define TX_ESC_CLK_DIVIDSION(x) UPDATE(x, 7, 0)
37 #define DPI_COLOR_CODING(x) UPDATE(x, 4, 2)
38 #define DPI_VID(x) UPDATE(x, 1, 0)
40 #define GEN_VID_RX(x) UPDATE(x, 6, 5)
57 #define VID_MODE_TYPE(x) UPDATE(x, 2, 1)
60 #define NULL_PKT_SIZE(x) UPDATE(x, 30, 21)
61 #define NUM_CHUNKS(x) UPDATE(x, 20, 11)
62 #define VID_PKT_SIZE(x) UPDATE(x, 10, 0)
80 #define HLINE_TIME(x) UPDATE(x, 31, 18)
[all …]
H A Dinno_video_combo_phy.c24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
49 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
50 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
63 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
65 #define REG_PREDIV(x) UPDATE(x, 4, 0)
68 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
71 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
73 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
76 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
78 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)
[all …]
H A Dinno_mipi_phy.c26 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) macro
55 #define FBDIV_HI(x) UPDATE(x, 5, 5)
57 #define PREDIV(x) UPDATE(x, 4, 0)
60 #define FBDIV_LO(x) UPDATE(x, 7, 0)
69 #define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
72 #define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
90 #define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
93 #define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
96 #define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
131 #define T_LPX(x) UPDATE(x, 5, 0)
[all …]
/rk3399_rockchip-uboot/doc/uImage.FIT/
H A Dupdate3.its2 * Example Automatic software update file.
12 update@1 {
22 update@2 {
33 update@3 {
H A Dupdate_uboot.its2 * Automatic software update for U-Boot
9 description = "Automatic U-Boot update";
13 update@1 {
/rk3399_rockchip-uboot/board/Marvell/db-88f6820-gp/
H A DREADME1 Update from original Marvell U-Boot to mainline U-Boot:
7 To update the SPI NOR flash, please use the following
11 sf update 2000000 0 60000
14 problems with the "sf update" command. This does not
/rk3399_rockchip-uboot/arch/x86/dts/
H A Dcougarcanyon2.dts32 update@0 {
35 update@1 {
38 update@2 {
41 update@3 {
44 update@4 {
/rk3399_rockchip-uboot/drivers/net/phy/
H A Dmscc.c145 /* Update LinkDetectCtrl default to optimized values */ in mscc_vsc8531_vsc8541_init_scripts()
158 /* Update VgaThresh100 defaults to optimized values */ in mscc_vsc8531_vsc8541_init_scripts()
172 /* Update VgaGain10 defaults to optimized values */ in mscc_vsc8531_vsc8541_init_scripts()
319 /* Update Reg23.12:11 */ in vsc8531_vsc8541_mac_config()
330 /* Update Reg20E2.11 */ in vsc8531_vsc8541_mac_config()
376 /* Reg20E2 - Update RGMII RX_Clk Skews. */ in vsc8531_config()
379 /* Reg20E2 - Update RGMII TX_Clk Skews. */ in vsc8531_config()
386 /* Reg27E2 - Update Clk Slew Rate. */ in vsc8531_config()
389 /* Reg27E2 - Update RMII Clk Out. */ in vsc8531_config()
392 /* Update Reg27E2 */ in vsc8531_config()
[all …]
/rk3399_rockchip-uboot/lib/
H A Dmembuff.c22 static int membuff_putrawflex(struct membuff *mb, int maxlen, bool update, in membuff_putrawflex() argument
46 /* update the head pointer to mark these bytes as written */ in membuff_putrawflex()
47 if (update) in membuff_putrawflex()
56 if (update) in membuff_putrawflex()
67 /* update the head pointer to mark these bytes as written */ in membuff_putrawflex()
68 if (update) in membuff_putrawflex()
76 int membuff_putraw(struct membuff *mb, int maxlen, bool update, char **data) in membuff_putraw() argument
82 size = membuff_putrawflex(mb, maxlen, update, &datap, &offset); in membuff_putraw()
99 int membuff_getraw(struct membuff *mb, int maxlen, bool update, char **data) in membuff_getraw() argument
120 if (update) in membuff_getraw()
[all …]
/rk3399_rockchip-uboot/drivers/power/domain/
H A Dtegra186-power-domain.c13 #define UPDATE BIT(0) macro
24 req.logic_state = UPDATE | on_state; in tegra186_power_domain_common()
25 req.sram_state = UPDATE | on_state; in tegra186_power_domain_common()
31 req.clock_state = UPDATE; in tegra186_power_domain_common()

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