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/optee_os/core/drivers/clk/sam/
H A Dat91_master.c32 static bool clk_master_ready(struct clk_master *master) in clk_master_ready() argument
34 uint32_t status = io_read32(master->base + AT91_PMC_SR); in clk_master_ready()
41 struct clk_master *master = clk->priv; in clk_master_enable() local
43 while (!clk_master_ready(master)) in clk_master_enable()
55 struct clk_master *master = clk->priv; in clk_master_div_get_rate() local
56 const struct clk_master_layout *layout = master->layout; in clk_master_div_get_rate()
57 const struct clk_master_charac *charac = master->charac; in clk_master_div_get_rate()
59 mckr = io_read32(master->base + master->layout->offset); in clk_master_div_get_rate()
68 IMSG("master clk div is underclocked"); in clk_master_div_get_rate()
70 IMSG("master clk div is overclocked"); in clk_master_div_get_rate()
[all …]
H A Dat91_clk.h96 /* Master */
191 /* Master */
/optee_os/core/arch/arm/plat-sam/
H A Dtz_matrix.h30 #define MATRIX_MCFG(n) (0x0000 + (n) * 4) /* Master Configuration Register */
35 #define MATRIX_MRCR 0x0100 /* Master Remap Control Register */
36 #define MATRIX_MEIER 0x0150 /* Master Error Interrupt Enable Register */
37 #define MATRIX_MEIDR 0x0154 /* Master Error Interrupt Disable Register */
38 #define MATRIX_MEIMR 0x0158 /* Master Error Interrupt Mask Register */
39 #define MATRIX_MESR 0x015c /* Master Error Status Register */
41 /* Master n Error Address Register */
H A Dsama7g5.h83 #define ID_MCAN0 61 /* Master CAN 0 (MCAN0) */
84 #define ID_MCAN1 62 /* Master CAN 1 (MCAN1) */
85 #define ID_MCAN2 63 /* Master CAN 2 (MCAN2) */
86 #define ID_MCAN3 64 /* Master CAN 3 (MCAN3) */
87 #define ID_MCAN4 65 /* Master CAN 4 (MCAN4) */
88 #define ID_MCAN5 66 /* Master CAN 5 (MCAN5) */
/optee_os/core/include/drivers/
H A Dls_i2c.h29 * Master / Slave Mode 0b - Slave mode 1b - Master mode
31 * on the bus and selects the master mode. When you change this field from 1 to
33 * master to slave. You should generate a STOP signal only if IBSR[IBIF]=1.
35 * master loses arbitration.
55 * If the I2C module is the current bus master, and you program RSTA=1, the I2C
58 * another master the result is loss of arbitration.
H A Dls_sec_mon.h26 * @lpmkcr: LP Master Key Control Register.
33 * @lpzmkr[8]: LP Zeroizable Master Key Registers.
H A Dstm32_risaf.h18 * firewall attributes of the master causing the illegal access. This function
H A Dimx_snvs.h12 /* Set the OTPMK Key as Master key */
H A Dstm32_risab.h24 * firewall attributes of the master causing the illegal access.
H A Dstm32_i2c.h81 I2C_MODE_MASTER, /* Communication in Master Mode */
235 * Send a data buffer in master mode on the I2C bus
249 * Receive a data buffer in master mode on the I2C bus
/optee_os/lib/libmbedtls/mbedtls/library/
H A Dssl_tls13_keys.h26 MBEDTLS_SSL_TLS1_3_LABEL(e_exp_master, "e exp master") \
27 MBEDTLS_SSL_TLS1_3_LABEL(res_master, "res master") \
28 MBEDTLS_SSL_TLS1_3_LABEL(exp_master, "exp master") \
217 * +-----> Derive-Secret(., "e exp master", ClientHello)
301 * \brief Derive TLS 1.3 application key material from the master secret.
307 * Master Secret
317 * +-----> Derive-Secret( ., "exp master",
329 * \param master_secret The master secret from which the application key
352 * \brief Derive TLS 1.3 resumption master secret from the master secret.
359 * \param application_secret The application secret from which the resumption master
[all …]
/optee_os/core/drivers/
H A Dimx_snvs.c65 * Return true if the master key is OTPMK, false otherwise.
75 * The master key selection might be done by the MASTER_KEY_SEL field in is_otpmk_selected()
89 * Return true if the master key selection is locked, false otherwise.
99 /* Set the Master key to use OTPMK and lock it. */
H A Dls_dspi.c24 0xC /* Clock and Transfer Attributes Register (in Master mode) */
26 0x10 /* Clock and Transfer Attributes Register (in Master mode) */
29 #define DSPI_PUSHR 0x34 /* PUSH TX FIFO Register In Master Mode */
44 #define DSPI_MCR_MSTR 0x80000000 /* Master/Slave Mode Select [0] */
499 * Configure master for DSPI controller
501 * mcr_val: value of master configuration register
506 DMSG("Set master state val=0x%x", mcr_val); in dspi_set_master_state()
523 /* Configure Master */ in ls_dspi_configure()
H A Dls_sec_mon.c30 * @lpmkcr: LP Master Key Control Register.
40 * @lpzmkr[0x8]: LP Zeroizable Master Key Registers.
/optee_os/core/arch/arm/plat-rzn1/
H A Dmain.c28 /* Timeout waiting for Master Idle Request Acknowledge */
89 /* Master Idle Request to the interconnect for CM3 */ in rzn1_cm3_start()
92 /* Wait for Master Idle Request Acknowledge for CM3 */ in rzn1_cm3_start()
/optee_os/core/include/kernel/
H A Drpc_io_i2c.h12 /* I2C master transfer mode */
18 /* I2C master transfer control flags */
/optee_os/core/include/drivers/sam/
H A Dat91_ddr.h154 /* Master Delay increment */
156 /* Master Delay decrement */
158 /* Master Delay Overflow */
160 /* Master Delay value */
/optee_os/core/arch/arm/kernel/
H A Drpc_io_i2c.c11 * @brief: I2C master transfer request to an I2C slave device.
15 * @param req: the secure world I2C master request
/optee_os/core/drivers/pm/sam/
H A Dpm_suspend.S31 * Wait until master clock is ready (after switching master clock source)
32 * @r_mckid: register holding master clock identifier
52 * Wait until master oscillator has stabilized.
407 /* Switch the master clock source to slow clock. */
584 /* Switch the master clock source to main clock */
622 /* Switch the master clock source to slow clock */
639 /* Switch the master clock source to main clock */
894 /* Save Master clock setting */
899 * Set master clock source to:
932 * Restore master clock setting
/optee_os/core/arch/arm/dts/
H A Dstm32mp15xx-dhcom-pdk2.dtsi185 frame-master = <&sgtl5000_tx_endpoint>;
186 bitclock-master = <&sgtl5000_tx_endpoint>;
192 frame-master = <&sgtl5000_rx_endpoint>;
193 bitclock-master = <&sgtl5000_rx_endpoint>;
/optee_os/core/lib/libefi/include/efi/
H A Dmmram.h41 …* https://github.com/samimujawar/edk2/blob/master/StandaloneMmPkg/Include/Guid/MmramMemoryRese…
/optee_os/core/include/
H A Doptee_rpc_cmd.h162 * Issue master requests (read and write operations) to an I2C chip.
169 * [in] value[1].a The I2C master control flags (ie, 10 bit address).
176 /* I2C master transfer modes */
180 /* I2C master control flags */
/optee_os/core/drivers/crypto/caam/hal/ls/registers/
H A Dctrl_regs.h12 /* Master Configuration */
/optee_os/core/drivers/crypto/caam/hal/imx_8m/registers/
H A Dctrl_regs.h12 /* Master Configuration */
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/registers/
H A Dctrl_regs.h12 /* Master Configuration */

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