Searched +full:lgm +full:- +full:clk (Results 1 – 12 of 12) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>13 Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides17 Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it23 const: intel,cgu-lgm28 '#clock-cells':32 - compatible[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"10 - Adrian Hunter <adrian.hunter@intel.com>13 - $ref: "mmc-controller.yaml#"14 - if:18 const: arasan,sdhci-5.121 - phys22 - phy-names23 - if:[all …]
1 # SPDX-License-Identifier: GPL-2.0-only2 obj-$(CONFIG_PMC_ATOM) += clk-pmc-atom.o3 obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE) += clk-fch.o4 clk-x86-lpss-objs := clk-lpt.o5 obj-$(CONFIG_X86_INTEL_LPSS) += clk-x86-lpss.o6 obj-$(CONFIG_CLK_LGM_CGU) += clk-cgu.o clk-cgu-pll.o clk-lgm.o
1 // SPDX-License-Identifier: GPL-2.07 #include <linux/clk-provider.h>10 #include <dt-bindings/clock/intel,lgm-clk.h>11 #include "clk-cgu.h"119 * It's more efficient to provide an explicit table due to non-linear223 * (network on chip peripheral clk) as critical clocks because425 struct device *dev = &pdev->dev; in lgm_cgu_probe()426 struct device_node *np = dev->of_node; in lgm_cgu_probe()432 return -ENOMEM; in lgm_cgu_probe()434 ctx->clk_data.num = CLK_NR_CLKS; in lgm_cgu_probe()[all …]
1 // SPDX-License-Identifier: GPL-2.011 #include <linux/clk.h>113 struct clk *freqclk;115 struct clk *clk; member150 spin_lock_irqsave(<q_port->lock, flags); in lqasc_start_tx()152 spin_unlock_irqrestore(<q_port->lock, flags); in lqasc_start_tx()159 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()165 struct tty_port *tport = &port->state->port; in lqasc_rx_chars()168 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_rx_chars()170 while (fifocnt--) { in lqasc_rx_chars()[all …]
1 // SPDX-License-Identifier: GPL-2.08 #include <linux/clk.h>48 struct clk *emmcclk;64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()67 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()75 rate = clk_get_rate(priv->emmcclk); in intel_emmc_phy_power()78 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); in intel_emmc_phy_power()88 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()91 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()102 ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG, in intel_emmc_phy_power()[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Intel Combo-PHY driver5 * Copyright (C) 2019-2020 Intel Corporation.9 #include <linux/clk.h>20 #include <dt-bindings/phy/phy.h>37 #define COMBO_PHY_ID(x) ((x)->parent->id)38 #define PHY_ID(x) ((x)->id)88 struct clk *core_clk;107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()[all …]
1 // SPDX-License-Identifier: GPL-2.09 #include <linux/clk.h>18 #include "pcie-designware.h"20 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)72 struct clk *core_clk;90 return readl(lpp->app_base + ofs); in pcie_app_rd()95 writel(val, lpp->app_base + ofs); in pcie_app_wr()101 pcie_update_bits(lpp->app_base, ofs, mask, val); in pcie_app_wr_mask()106 return dw_pcie_readl_dbi(&lpp->pci, ofs); in pcie_rc_cfg_rd()111 dw_pcie_writel_dbi(&lpp->pci, ofs, val); in pcie_rc_cfg_wr()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>9 * Based on sdhci-of-esdhc.c18 #include <linux/clk-provider.h>25 #include <linux/firmware/xlnx-zynqmp.h>28 #include "sdhci-cqhci.h"29 #include "sdhci-pltfm.h"56 * On some SoCs the syscon area has a feature where the upper 16-bits of57 * each 32-bit register act as a write mask for the lower 16-bits. This allows65 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>10 #include <linux/clk.h>141 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */168 struct clk *spi_clk;169 struct clk *fpi_clk;190 return __raw_readl(spi->regbase + reg); in lantiq_ssc_readl()196 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_writel()202 u32 val = __raw_readl(spi->regbase + reg); in lantiq_ssc_maskl()[all …]
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