Searched +full:combined +full:- +full:power +full:- +full:req (Results 1 – 25 of 62) sorted by relevance
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1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Tegra Power Management Controller (PMC)10 - Thierry Reding <thierry.reding@gmail.com>11 - Jonathan Hunter <jonathanh@nvidia.com>16 - nvidia,tegra20-pmc17 - nvidia,tegra20-pmc18 - nvidia,tegra30-pmc[all …]
4 * SPDX-License-Identifier: GPL-2.0+19 * The mailbox hardware supports passing 32-bit values back and forth.24 * example, the messages on the power management channel are a bitmask of25 * devices whose power should be enabled.27 * The property mailbox channel passes messages that contain the (16-byte29 * the VC for processing, is modified in-place by the VC, and the address then35 * combined together into a single message buffer. This file defines structs58 /* Lower 4-bits are channel ID */80 (_m_)->hdr.buf_size = sizeof(*(_m_)); \81 (_m_)->hdr.code = 0; \[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Alexandre Torgue <alexandre.torgue@st.com>11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>12 - Jose Abreu <joabreu@synopsys.com>23 - snps,dwmac24 - snps,dwmac-3.50a25 - snps,dwmac-3.61026 - snps,dwmac-3.70a[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */21 #define SCLP_EVTYP_MASK(T) (1UL << (sizeof(sccb_mask_t) * BITS_PER_BYTE - (T)))135 sccb_get_mask(__sccb->masks, __sccb->mask_length, i); \146 sccb_set_mask(__sccb->masks, __sccb->mask_length, i, val); \159 u8 reserved[4096 - 16];163 struct sccb_header header; /* 0-7 */164 u16 rnmax; /* 8-9 */166 u8 _pad_11[16 - 11]; /* 11-15 */167 u16 ncpurl; /* 16-17 */168 u16 cpuoff; /* 18-19 */[all …]
15 #include "clk-kona.h"20 #include <linux/clk-provider.h>25 * "Normal", and "Turbo".) A lower policy number has lower power35 /* Produces a mask of set bits covering a range of a 32-bit value */38 return ((1 << width) - 1) << shift; in bitfield_mask()60 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()70 u64 combined; in scaled_div_build() local75 combined = (u64)div_value * BILLION + billionths; in scaled_div_build()76 combined <<= div->u.s.frac_width; in scaled_div_build()78 return DIV_ROUND_CLOSEST_ULL(combined, BILLION); in scaled_div_build()[all …]
1 .. SPDX-License-Identifier: GPL-2.022 - Ulisses Alonso Camaró <uaca@i.hate.spam.alumni.uv.es>23 - Johann Baudy67 [setup] socket() -------> creation of the capture socket68 setsockopt() ---> allocation of the circular buffer (ring)70 mmap() ---------> mapping of the allocated buffer to the73 [capture] poll() ---------> to wait for incoming packets75 [shutdown] close() --------> destruction of the capture socket and88 supported and a link level pseudo-header is provided107 [setup] socket() -------> creation of the transmission socket[all …]
1 // SPDX-License-Identifier: GPL-2.02 /* Copyright(c) 1999 - 2018 Intel Corporation. */17 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X550_x()18 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x()19 struct ixgbe_link_info *link = &hw->link; in ixgbe_get_invariants_X550_x()24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_get_invariants_X550_x()25 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x()27 link->addr = IXGBE_CS4227; in ixgbe_get_invariants_X550_x()34 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x_fw()39 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x_fw()[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2005 Lothar Wassmann <LW@KARO-electronics.de>21 * 2. Implement platform-specific delay function possibly22 * combined with configuring the memory controller; see99 #define DRIVER_VERSION "2005-04-04"105 static const char hcd_name[] = "isp1362-hcd";110 /*-------------------------------------------------------------------------*/113 * When called from the interrupthandler only isp1362_hcd->irqenb is modified,114 * since the interrupt handler will write isp1362_hcd->irqenb to HCuPINT upon121 if ((isp1362_hcd->irqenb | mask) == isp1362_hcd->irqenb) in isp1362_enable_int()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.12 #define pr_fmt(fmt) "tegra-pmc: " fmt14 #include <linux/arm-smccc.h>16 #include <linux/clk-provider.h>18 #include <linux/clk/clk-conf.h>36 #include <linux/pinctrl/pinconf-generic.h>51 #include <dt-bindings/interrupt-controller/arm-gic.h>52 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>53 #include <dt-bindings/gpio/tegra186-gpio.h>[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */6 * Copyright (C) 1999-2017, Broadcom Corporation27 * <<Broadcom-WL-IPTag/Open:>>29 * $Id: sdioh.h 514727 2014-11-12 03:02:48Z $87 /* preset-indiv regs */116 /* Note: for sdio-2.0 case, this mask has to be 6 bits, but msb 2117 bits are reserved. going ahead with 8 bits, as it is req for 3.0157 #define CAP3_SDR50_SUP_S (32 - CAP3_MSBits_OFFSET)160 #define CAP3_SDR104_SUP_S (33 - CAP3_MSBits_OFFSET)163 #define CAP3_DDR50_SUP_S (34 - CAP3_MSBits_OFFSET)[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */10 * Copyright (C) 1999-2017, Broadcom Corporation29 * <<Broadcom-WL-IPTag/Open:>>31 * $Id: wlioctl.h 677952 2017-01-05 23:25:28Z $91 (sizeof(wl_dfs_forced_t) + (((n) < 1) ? (0) : (((n) - 1)* sizeof(chanspec_t))))107 #define DFS_SCAN_S_IDLE -1193 * will see OBSS, [means that, we false detected that OBSS-is-gone294 * Per-BSS information structure.396 #define WL_GSCAN_INFO_FIXED_FIELD_SIZE (sizeof(wl_gscan_bss_info_t) - sizeof(wl_bss_info_t))546 #define WL_EXTDSCAN_PARAMS_FIXED_SIZE (sizeof(wl_extdscan_params_t) - sizeof(chan_scandata_t))[all …]
7 * Copyright (C) 1999-2017, Broadcom Corporation28 * <<Broadcom-WL-IPTag/Open:>>30 * $Id: sdioh.h 514727 2014-11-12 03:02:48Z $88 /* preset-indiv regs */116 /* Note: for sdio-2.0 case, this mask has to be 6 bits, but msb 2117 bits are reserved. going ahead with 8 bits, as it is req for 3.0156 #define CAP3_SDR50_SUP_S (32 - CAP3_MSBits_OFFSET)159 #define CAP3_SDR104_SUP_S (33 - CAP3_MSBits_OFFSET)162 #define CAP3_DDR50_SUP_S (34 - CAP3_MSBits_OFFSET)166 #define CAP3_30CLKCAP_S (32 - CAP3_MSBits_OFFSET)[all …]
11 * Copyright (C) 1999-2017, Broadcom Corporation32 * <<Broadcom-WL-IPTag/Open:>>61 * BCME_.. error codes are extended by various features - e.g. FTM, NAN, SAE etc.68 * The error codes -4096 ... -5119 are reserved for firmware signing.70 * Next available (inclusive) range: [-6*1024 + 1, -5*1024]75 /* 11ax trigger frame format - versioning info */122 (sizeof(wl_dfs_forced_t) + (((n) < 1) ? (0) : (((n) - 1)* sizeof(chanspec_t))))138 #define DFS_SCAN_S_IDLE -1253 * will see OBSS, [means that, we false detected that OBSS-is-gone353 * Per-BSS information structure.[all …]
22 * <<Broadcom-WL-IPTag/Dual:>>94 /* preset-indiv regs */122 /* Note: for sdio-2.0 case, this mask has to be 6 bits, but msb 2123 bits are reserved. going ahead with 8 bits, as it is req for 3.0162 #define CAP3_SDR50_SUP_S (32 - CAP3_MSBits_OFFSET)165 #define CAP3_SDR104_SUP_S (33 - CAP3_MSBits_OFFSET)168 #define CAP3_DDR50_SUP_S (34 - CAP3_MSBits_OFFSET)172 #define CAP3_30CLKCAP_S (32 - CAP3_MSBits_OFFSET)175 #define CAP3_DRIVTYPE_A_S (36 - CAP3_MSBits_OFFSET)178 #define CAP3_DRIVTYPE_C_S (37 - CAP3_MSBits_OFFSET)[all …]
26 * <<Broadcom-WL-IPTag/Dual:>>62 * BCME_.. error codes are extended by various features - e.g. FTM, NAN, SAE etc.69 * The error codes -4096 ... -5119 are reserved for firmware signing.71 * Next available (inclusive) range: [-8*1024 + 1, -7*1024]76 /* 11ax trigger frame format - versioning info */122 (sizeof(wl_dfs_forced_t) + (((n) < 1) ? (0) : (((n) - 1)* sizeof(chanspec_t))))142 #define DFS_SCAN_S_IDLE -1227 * will see OBSS, [means that, we false detected that OBSS-is-gone449 uint32 timestamp[2]; /* Beacon Timestamp for FAKEAP req */500 uint32 timestamp[2]; /* Beacon Timestamp for FAKEAP req */[all …]
8 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation. All rights reserved.9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-649730 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation. All rights reserved.31 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH32 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH75 #include "iwl-op-mode.h"76 #include "iwl-trans.h"77 #include "fw/notif-wait.h"[all …]
... MAX_PEER_WLU=%d CURRENT MAXIMUM PEERS = %d - Link Power Control parameters - tp_ratio_thresh = %d rate_stab_thresh ...
7 * Copyright (C) 2008-2017, Marvell International Ltd.14 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the15 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.17 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE119 (_adapter->fw_cap_info & FW_MULTI_BANDS_SUPPORT)122 ((_adapter->fw_cap_info >> 8) & ALL_802_11_BANDS)145 /** Default power save mode */278 #define CAL_SNR(RSSI, NF) ((t_s16)((t_s16)(RSSI) - (t_s16)(NF)))305 /** TLV type : Power constraint */308 /** TLV type : Power capability */[all …]
8 * Copyright 2008-2022 NXP15 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the16 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.18 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE136 (_adapter->fw_cap_info & FW_MULTI_BANDS_SUPPORT)143 (((((_adapter->fw_cap_info & 0x3000) << 1) | \144 (_adapter->fw_cap_info & ~0xF000)) >> \160 /** Default power save mode */297 #define CAL_SNR(RSSI, NF) ((t_s16)((t_s16)(RSSI) - (t_s16)(NF)))321 /** TLV type : Power constraint */[all …]
52 #define BTC_BUSY2IDLE_THRES 10000 /* wait time for WL busy-to-idle, 10sec = 10000ms */54 /* reserved 5 rf_trx_para level for non-freerun case */56 /* Define MAC-Related Reg Addr and Bitmap109 #define BTC_WL_RSSI_MAX_BTG 70 /* for BTG co-rx Hi-RSSI thres */136 rtw_hal_mac_coex_reg_write(btc->hal, offset, val)139 rtw_hal_read_rf_reg(btc->hal, path, addr, mask);141 rtw_hal_write_rf_reg(btc->hal, path, addr, mask, data)146 (hal_mem_cmp(btc->hal, btc->dm.run_reason, r, _os_strlen((u8*)r))? 0:1)148 hal_mem_cpy(btc->hal, dst, src, BTC_RSN_MAXLEN)150 hal_mem_cpy(btc->hal, dst, src, BTC_ACT_MAXLEN)[all …]