1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _HAL_BTC_H_ 16 #define _HAL_BTC_H_ 17 18 #include "halbtc_fw.h" 19 #include "halbtc_dbg_cmd.h" 20 21 #ifdef CONFIG_RTL8852A 22 #define BTC_8852A_SUPPORT 23 #endif 24 25 #ifdef CONFIG_RTL8852B 26 #define BTC_8852B_SUPPORT 27 #endif 28 29 #ifdef CONFIG_RTL8852C 30 #define BTC_8852C_SUPPORT 31 #endif 32 33 #define BTC_GPIO_DBG_EN 1 34 #define BTC_CX_FW_OFFLOAD 0 35 #define BTC_PHY_MAX 2 36 #define BTC_NON_SHARED_ANT_FREERUN 0 37 38 #define BTC_SCBD_REWRITE_DELAY 1000 39 #define BTC_MSG_MAXLEN 200 40 #define BTC_POLICY_MAXLEN 512 41 #define BTC_HUBMSG_MAXLEN 512 42 #define BTC_RPT_PERIOD 2000 43 #define BTC_RSN_MAXLEN 32 44 #define BTC_ACT_MAXLEN 32 45 #define BTC_DELAYED_PERIODIC_TIME 2000 /* 2000ms, delayed to start periodic timer */ 46 #define BTC_PERIODIC_TIME 100 /* 100ms, must be non zero and < 2000 */ 47 #define BTC_WRFK_MAXT 300 /* WL RFK 300ms */ 48 #define BTC_BRFK_MAXT 800 /* BT RFK 800ms */ 49 #define BTC_SPECPKT_MAXT 4000 /* special pkt unit: 4000ms */ 50 #define BTC_A2DP_RESUME_MAXT 16000 /* for A2DP resume, 16sec = 16000ms */ 51 #define BTC_RPT_HDR_SIZE 3 52 #define BTC_BUSY2IDLE_THRES 10000 /* wait time for WL busy-to-idle, 10sec = 10000ms */ 53 #define BTC_WL_DEF_TX_PWR 255 54 /* reserved 5 rf_trx_para level for non-freerun case */ 55 #define BTC_LEVEL_ID_OFFSET 5 56 /* Define MAC-Related Reg Addr and Bitmap 57 * These definitions should be removed if MACAPI support. 58 */ 59 #define BTC_DM_MAXSTEP 30 60 61 #define BTC_LEAK_AP_TH 10 62 #define BTC_CYSTA_CHK_PERIOD 100 63 64 #define BTC_SCC_CYCLE 100 65 #define BTC_NULL1_EBT_EARLY_T 10 66 67 #define R_BTC_CFG 0xDA00 68 #define R_BTC_WL_PRI_MSK 0xDA10 69 #define R_BTC_BREAK_TABLE 0xDA2C 70 #define R_BTC_BT_COEX_MSK_TABLE 0xDA30 71 #define R_BTC_CSR_MODE 0xDA40 72 #define R_BTC_BT_STAST_HIGH 0xDA44 73 #define R_BTC_BT_STAST_LOW 0xDA48 74 75 #define B_BTC_WL_SRC BIT(0) 76 #define B_BTC_DIS_BTC_CLK_G BIT(2) 77 #define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3) 78 #define B_BTC_PRI_MASK_RXCCK_V1 BIT(28) 79 #define B_BTC_DBG_GNT_WL_BT BIT(27) 80 #define B_BTC_BT_CNT_REST BIT(16) 81 #define B_BTC_PTA_WL_PRI_MASK_BCNQ BIT(8) 82 #define B_BTC_PTA_WL_PRI_MASK_MGQ BIT(4) 83 84 struct btc_t; 85 86 #define NM_EXEC false 87 #define FC_EXEC true 88 89 #ifndef ARRAY_SIZE 90 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 91 #endif 92 93 #ifndef BIT 94 #define BIT(x) (1 << (x)) 95 #endif 96 97 #define bMASKDW 0xffffffff 98 #define bMASKHW 0xffff0000 99 #define bMASKLW 0x0000ffff 100 #define bMASKB0 0x000000ff 101 #define bMASKB1 0x0000ff00 102 #define bMASKB2 0x00ff0000 103 #define bMASKB3 0xff000000 104 #define bMASKRF 0x000fffff 105 106 #define BTC_WL_RSSI_THMAX 4 107 #define BTC_BT_RSSI_THMAX 4 108 109 #define BTC_WL_RSSI_MAX_BTG 70 /* for BTG co-rx Hi-RSSI thres */ 110 111 #define BTC_TDMA_WLROLE_MAX 2 112 #define BTC_TDMA_BTHID_MAX 2 113 #define BTC_FREERUN_ANTISO_MIN 30 114 #define BTC_BT_RX_NORMAL_LVL 7 115 116 #define BTC_BT_INFO_LEN 6 117 #define BTC_B1_MAX 250 /* unit:ms, used for Max A2DP retry adjust */ 118 119 #define BTC_COEX_RTK_MODE 0 120 #define BTC_COEX_CSR_MODE 1 121 #define BTC_COEX_INNER 0 122 #define BTC_COEX_OUTPUT 1 123 #define BTC_COEX_INPUT 2 124 125 #define BTC_BLINK_NOCONNECT 0 126 #define BTC_WL_NONE 0 127 #define BTC_CHK_HANG_MAX 3 128 #define BTC_CHK_WLSLOT_DRIFT_MAX 15 129 #define BTC_CHK_BTSLOT_DRIFT_MAX 15 130 131 #define BTC_RFK_PATH_MAP 0xf 132 #define BTC_RFK_PHY_MAP 0x30 133 #define BTC_RFK_BAND_MAP 0xc0 134 135 #define _write_cx_reg(btc, offset, val) \ 136 rtw_hal_mac_coex_reg_write(btc->hal, offset, val) 137 138 #define _read_wl_rf_reg(btc, path, addr, mask) \ 139 rtw_hal_read_rf_reg(btc->hal, path, addr, mask); 140 #define _write_wl_rf_reg(btc, path, addr, mask, data) \ 141 rtw_hal_write_rf_reg(btc->hal, path, addr, mask, data) 142 143 #define _update_poicy hal_btc_fw_set_policy 144 145 #define run_rsn(r) \ 146 (hal_mem_cmp(btc->hal, btc->dm.run_reason, r, _os_strlen((u8*)r))? 0:1) 147 #define _rsn_cpy(dst, src) \ 148 hal_mem_cpy(btc->hal, dst, src, BTC_RSN_MAXLEN) 149 #define _act_cpy(dst, src) \ 150 hal_mem_cpy(btc->hal, dst, src, BTC_ACT_MAXLEN) 151 152 #define _tdma_cmp(dst, src) \ 153 hal_mem_cmp(btc->hal, dst, src, sizeof(struct fbtc_tdma)) 154 #define _tdma_cpy(dst, src) \ 155 hal_mem_cpy(btc->hal, dst, src, sizeof(struct fbtc_tdma)) 156 #define _tdma_set(tp,rxflc,txflc,wtg,lek,ext,flc_role) \ 157 do { \ 158 btc->dm.tdma.type = tp;\ 159 btc->dm.tdma.rxflctrl = rxflc; \ 160 btc->dm.tdma.txflctrl = txflc; \ 161 btc->dm.tdma.wtgle_n = wtg; \ 162 btc->dm.tdma.leak_n = lek; \ 163 btc->dm.tdma.ext_ctrl = ext; \ 164 btc->dm.tdma.rxflctrl_role = flc_role; \ 165 } while (0) 166 #define _tdma_set_rxflctrl(rxflc) btc->dm.tdma.rxflctrl = rxflc 167 #define _tdma_set_txflctrl(txflc) btc->dm.tdma.txflctrl = txflc 168 #define _tdma_set_flctrl_role(role) btc->dm.tdma.rxflctrl_role = role 169 #define _tdma_set_tog(wtg) btc->dm.tdma.wtgle_n = wtg 170 #define _tdma_set_lek(lek) btc->dm.tdma.leak_n = lek 171 172 #define _slot_cmp(dst, src) \ 173 hal_mem_cmp(btc->hal, dst, src, sizeof(struct fbtc_slot)) 174 #define _slot_cpy(dst, src) \ 175 hal_mem_cpy(btc->hal, dst, src, sizeof(struct fbtc_slot)) 176 #define _slots_cpy(dst, src) \ 177 hal_mem_cpy(btc->hal, dst, src, CXST_MAX*sizeof(struct fbtc_slot)) 178 #define _slot_set(sid,dura,tbl,type) \ 179 do { \ 180 btc->dm.slot[sid].dur = dura;\ 181 btc->dm.slot[sid].cxtbl = tbl; \ 182 btc->dm.slot[sid].cxtype = type; \ 183 } while (0) 184 #define _slot_set_dur(sid,dura) btc->dm.slot[sid].dur = dura 185 #define _slot_set_tbl(sid,tbl) btc->dm.slot[sid].cxtbl = tbl 186 #define _slot_set_type(sid,type) btc->dm.slot[sid].cxtype = type 187 188 enum btc_wl_gpio_debug { 189 BTC_DBG_GNT_BT = 0, 190 BTC_DBG_GNT_WL = 1, 191 /* The following signals should 0-1 tiggle by each function-call */ 192 BTC_DBG_BCN_EARLY = 2, 193 BTC_DBG_WL_NULL0 = 3, 194 BTC_DBG_WL_NULL1 = 4, 195 BTC_DBG_WL_RXISR = 5, 196 BTC_DBG_TDMA_ENTRY = 6, 197 BTC_DBG_A2DP_EMPTY = 7, 198 BTC_DBG_BT_RETRY = 8, 199 /* The following signals should 0-1 tiggle by state L/H */ 200 BTC_DBG_BT_RELINK = 9, 201 BTC_DBG_SLOT_WL = 10, 202 BTC_DBG_SLOT_BT = 11, 203 BTC_DBG_WL_RFK = 12, 204 BTC_DBG_BT_RFK = 13, 205 /* The following signals should appear only 1 "Hi" at same time */ 206 BTC_DBG_SLOT_B2W = 14, 207 BTC_DBG_SLOT_W1 = 15, 208 BTC_DBG_SLOT_W2 = 16, 209 BTC_DBG_SLOT_W2B = 17, 210 BTC_DBG_SLOT_B1 = 18, 211 BTC_DBG_SLOT_B2 = 19, 212 BTC_DBG_SLOT_B3 = 20, 213 BTC_DBG_SLOT_B4 = 21, 214 BTC_DBG_SLOT_LK = 22, 215 BTC_DBG_SLOT_E2G = 23, 216 BTC_DBG_SLOT_E5G = 24, 217 BTC_DBG_SLOT_EBT = 25, 218 BTC_DBG_SLOT_ENULL = 26, 219 BTC_DBG_SLOT_WLK = 27, 220 BTC_DBG_SLOT_W1FDD = 28, 221 BTC_DBG_SLOT_B1FDD = 29, 222 BTC_DBG_BT_CHANGE = 30 223 }; 224 225 enum btc_cx_run_info { 226 BTC_CXR_WSCBD = 0, 227 BTC_CXR_RESULT, 228 BTC_CXR_MAX 229 }; 230 231 enum btc_bt_rfk_state { 232 BTC_BRFK_STOP = 0, 233 BTC_BRFK_START = 1 234 }; 235 236 enum btc_wl_rfk_state { 237 BTC_WRFK_STOP = 0, 238 BTC_WRFK_START = 1, 239 BTC_WRFK_ONESHOT_START = 2, 240 BTC_WRFK_ONESHOT_STOP = 3 241 }; 242 243 enum btc_wl_rfk_result { 244 BTC_WRFK_REJECT = 0, 245 BTC_WRFK_ALLOW = 1 246 }; 247 248 enum { 249 BTC_LPS_OFF = 0, 250 BTC_LPS_RF_OFF = 1, 251 BTC_LPS_RF_ON = 2 252 }; 253 254 enum { 255 BTC_CTRL_BY_BT = 0, 256 BTC_CTRL_BY_WL 257 }; 258 259 enum { 260 BTC_3CX_NONE = 0, 261 BTC_3CX_LTE = 1, 262 BTC_3CX_ZB = 2, 263 BTC_3CX_MAX 264 }; 265 266 enum { 267 BTC_PRI_MASK_RX_RESP = 0, 268 BTC_PRI_MASK_TX_RESP, 269 BTC_PRI_MASK_BEACON, 270 BTC_PRI_MASK_RX_CCK, 271 BTC_PRI_MASK_TX_MNGQ, 272 BTC_PRI_MASK_MAX 273 }; 274 275 enum { 276 BTC_INIT_NORMAL, 277 BTC_INIT_WLONLY, 278 BTC_INIT_WLOFF 279 }; 280 281 enum { 282 BTC_BRANCH_MAIN = 0, 283 BTC_BRANCH_HP, 284 BTC_BRANCH_LENOVO, 285 BTC_BRANCH_HUAWEI, 286 BTC_BRANCH_MAX 287 }; 288 289 enum { 290 BTC_STR_ROLE = 0, 291 BTC_STR_MROLE, 292 BTC_STR_REG, 293 BTC_STR_SLOT, 294 BTC_STR_TDMA, 295 BTC_STR_TRACE, 296 BTC_STR_BRANCH, 297 BTC_STR_RXFLCTRL, 298 BTC_STR_WLLINK, 299 BTC_STR_ANTPATH, 300 BTC_STR_GDBG, 301 BTC_STR_CHIPID, 302 BTC_STR_EVENT, 303 BTC_STR_WLMODE, 304 BTC_STR_WLBW, 305 BTC_STR_RFTYPE, 306 BTC_STR_POLICY, 307 BTC_STR_MSTATE, 308 BTC_STR_RATE, 309 BTC_STR_POLUT, 310 BTC_STR_MAX 311 }; 312 313 enum { 314 BTC_WL = 0, 315 BTC_BT, 316 BTC_ZB, 317 BTC_LTE, 318 BTC_MAX 319 }; 320 321 enum { 322 BTC_BT_SS_GROUP = 0x0, 323 BTC_BT_TX_GROUP = 0x2, 324 BTC_BT_RX_GROUP = 0x3, 325 BTC_BT_MAX_GROUP, 326 }; 327 328 enum btc_rssi_st { 329 BTC_RSSI_ST_LOW = 0x0, 330 BTC_RSSI_ST_HIGH, 331 BTC_RSSI_ST_STAY_LOW, 332 BTC_RSSI_ST_STAY_HIGH, 333 BTC_RSSI_ST_MAX 334 }; 335 336 #define BTC_RSSI_HIGH(_rssi_) \ 337 ((_rssi_ == BTC_RSSI_ST_HIGH || _rssi_ == BTC_RSSI_ST_STAY_HIGH)? 1:0) 338 #define BTC_RSSI_LOW(_rssi_) \ 339 ((_rssi_ == BTC_RSSI_ST_LOW || _rssi_ == BTC_RSSI_ST_STAY_LOW)? 1:0) 340 #define BTC_RSSI_CHANGE(_rssi_) \ 341 ((_rssi_ == BTC_RSSI_ST_LOW || _rssi_ == BTC_RSSI_ST_HIGH)? 1:0) 342 343 enum btc_coex_info_map_en { 344 BTC_COEX_INFO_CX = BIT(0), 345 BTC_COEX_INFO_WL = BIT(1), 346 BTC_COEX_INFO_BT = BIT(2), 347 BTC_COEX_INFO_DM = BIT(3), 348 BTC_COEX_INFO_MREG = BIT(4), 349 BTC_COEX_INFO_SUMMARY = BIT(5), 350 BTC_COEX_INFO_ALL = 0xff 351 }; 352 353 /* list all-chip scoreboard definition, remap at chip file */ 354 enum btc_w2b_scoreboard { 355 BTC_WSCB_ACTIVE = BIT(0), 356 BTC_WSCB_ON = BIT(1), 357 BTC_WSCB_SCAN = BIT(2), 358 BTC_WSCB_UNDERTEST = BIT(3), 359 BTC_WSCB_RXGAIN = BIT(4), /* set BT LNA constrain for free-run */ 360 BTC_WSCB_WLBUSY = BIT(7), 361 BTC_WSCB_EXTFEM = BIT(8), 362 BTC_WSCB_TDMA = BIT(9), 363 BTC_WSCB_FIX2M = BIT(10), 364 BTC_WSCB_WLRFK = BIT(11), 365 BTC_WSCB_RXSCAN_PRI = BIT(12), /* set BT Rx-Scan PTA pri */ 366 BTC_WSCB_BT_HILNA = BIT(13), /* 1: request BT use Hi-LNA table for BTG */ 367 BTC_WSCB_BTLOG = BIT(14), /* open BT log */ 368 BTC_WSCB_ALL = 0xffffff /* driver only use bit0~23 */ 369 }; 370 371 enum btc_b2w_scoreboard { 372 BTC_BSCB_ACT = BIT(0), 373 BTC_BSCB_ON = BIT(1), 374 BTC_BSCB_WHQL = BIT(2), 375 BTC_BSCB_BT_S1 = BIT(3), /* 1-> BT at S1, 0-> BT at S0 */ 376 BTC_BSCB_A2DP_ACT = BIT(4), 377 BTC_BSCB_RFK_RUN = BIT(5), 378 BTC_BSCB_RFK_REQ = BIT(6), 379 BTC_BSCB_LPS = BIT(7), 380 BTC_BSCB_WLRFK = BIT(11), 381 BTC_BSCB_BT_HILNA = BIT(13), /* reply if BT use Hi-LNA table for BTG */ 382 BTC_BSCB_BT_CONNECT = BIT(16), /* If any BT connected */ 383 BTC_BSCB_PATCH_CODE = BIT(30), /* BT use 1: patch code 2:ROM code */ 384 BTC_BSCB_ALL = 0x7fffffff 385 }; 386 387 enum btc_bt_link_status { 388 BTC_BLINK_CONNECT = BIT(0), 389 BTC_BLINK_BLE_CONNECT = BIT(1), 390 BTC_BLINK_ACL_BUSY = BIT(2), 391 BTC_BLINK_SCO_BUSY = BIT(3), 392 BTC_BLINK_MESH_BUSY = BIT(4), 393 BTC_BLINK_INQ_PAGE = BIT(5) 394 }; 395 396 enum { 397 BTC_DCNT_RUN = 0x0, 398 BTC_DCNT_CX_RUNINFO, 399 BTC_DCNT_RPT, 400 BTC_DCNT_RPT_FREEZE, 401 BTC_DCNT_CYCLE, 402 BTC_DCNT_CYCLE_FREEZE, 403 BTC_DCNT_W1, 404 BTC_DCNT_W1_FREEZE, 405 BTC_DCNT_B1, 406 BTC_DCNT_B1_FREEZE, 407 BTC_DCNT_TDMA_NONSYNC, 408 BTC_DCNT_SLOT_NONSYNC, 409 BTC_DCNT_BTCNT_FREEZE, 410 BTC_DCNT_WL_SLOT_DRIFT, 411 BTC_DCNT_WL_STA_LAST, 412 BTC_DCNT_BT_SLOT_DRIFT, 413 BTC_DCNT_MAX 414 }; 415 416 enum { 417 BTC_NCNT_POWER_ON = 0x0, 418 BTC_NCNT_POWER_OFF, 419 BTC_NCNT_INIT_COEX, 420 BTC_NCNT_SCAN_START, 421 BTC_NCNT_SCAN_FINISH, 422 BTC_NCNT_SPECIAL_PACKET, 423 BTC_NCNT_SWITCH_BAND, 424 BTC_NCNT_RFK_TIMEOUT, 425 BTC_NCNT_SHOW_COEX_INFO, 426 BTC_NCNT_ROLE_INFO, 427 BTC_NCNT_CONTROL, 428 BTC_NCNT_RADIO_STATE, 429 BTC_NCNT_CUSTOMERIZE, 430 BTC_NCNT_WL_RFK, 431 BTC_NCNT_WL_STA, 432 BTC_NCNT_FWINFO, 433 BTC_NCNT_TIMER, 434 BTC_NCNT_MAX 435 }; 436 437 enum btc_wl_state_cnt { 438 BTC_WCNT_SCANAP = 0x0, 439 BTC_WCNT_DHCP, 440 BTC_WCNT_EAPOL, 441 BTC_WCNT_ARP, 442 BTC_WCNT_SCBDUPDATE, 443 BTC_WCNT_RFK_REQ, 444 BTC_WCNT_RFK_GO, 445 BTC_WCNT_RFK_REJECT, 446 BTC_WCNT_RFK_TIMEOUT, 447 BTC_WCNT_CH_UPDATE, 448 BTC_WCNT_MAX 449 }; 450 451 enum btc_bt_state_cnt { 452 BTC_BCNT_RETRY = 0x0, 453 BTC_BCNT_REINIT, 454 BTC_BCNT_REENABLE, 455 BTC_BCNT_SCBDREAD, 456 BTC_BCNT_RELINK, 457 BTC_BCNT_IGNOWL, 458 BTC_BCNT_INQPAG, 459 BTC_BCNT_INQ, 460 BTC_BCNT_PAGE, 461 BTC_BCNT_ROLESW, 462 BTC_BCNT_AFH, 463 BTC_BCNT_INFOUPDATE, 464 BTC_BCNT_INFOSAME, 465 BTC_BCNT_SCBDUPDATE, 466 BTC_BCNT_HIPRI_TX, 467 BTC_BCNT_HIPRI_RX, 468 BTC_BCNT_LOPRI_TX, 469 BTC_BCNT_LOPRI_RX, 470 BTC_BCNT_POLUT, 471 BTC_BCNT_RATECHG, 472 BTC_BCNT_MAX 473 }; 474 475 enum btc_wl_link_mode { 476 BTC_WLINK_NOLINK = 0x0, 477 BTC_WLINK_2G_STA, 478 BTC_WLINK_2G_AP, 479 BTC_WLINK_2G_GO, 480 BTC_WLINK_2G_GC, 481 BTC_WLINK_2G_SCC, 482 BTC_WLINK_2G_MCC, 483 BTC_WLINK_25G_MCC, 484 BTC_WLINK_25G_DBCC, 485 BTC_WLINK_5G, 486 BTC_WLINK_2G_NAN, 487 BTC_WLINK_OTHER, 488 BTC_WLINK_MAX 489 }; 490 491 enum btc_wl_mrole_type { 492 BTC_WLMROLE_NONE = 0x0, 493 BTC_WLMROLE_STA_GC, 494 BTC_WLMROLE_STA_GC_NOA, 495 BTC_WLMROLE_STA_GO, 496 BTC_WLMROLE_STA_GO_NOA, 497 BTC_WLMROLE_STA_STA, 498 BTC_WLMROLE_MAX 499 }; 500 501 enum { 502 BTC_BTINFO_L0 = 0, 503 BTC_BTINFO_L1, 504 BTC_BTINFO_L2, 505 BTC_BTINFO_L3, 506 BTC_BTINFO_H0, 507 BTC_BTINFO_H1, 508 BTC_BTINFO_H2, 509 BTC_BTINFO_H3, 510 BTC_BTINFO_MAX 511 }; 512 513 struct btc_btinfo_lb2 { 514 u8 connect: 1; 515 u8 sco_busy: 1; 516 u8 inq_pag: 1; 517 u8 acl_busy: 1; 518 u8 hfp: 1; 519 u8 hid: 1; 520 u8 a2dp: 1; 521 u8 pan: 1; 522 }; 523 524 struct btc_btinfo_lb3 { 525 u8 retry: 4; 526 u8 cqddr: 1; 527 u8 inq: 1; 528 u8 mesh_busy: 1; 529 u8 pag: 1; 530 }; 531 532 struct btc_btinfo_hb0 { 533 u8 rssi; 534 }; 535 536 struct btc_btinfo_hb1 { 537 u8 ble_connect: 1; 538 u8 reinit: 1; 539 u8 relink: 1; 540 u8 igno_wl: 1; 541 u8 voice: 1; 542 u8 ble_scan: 1; 543 u8 role_sw: 1; 544 u8 multi_link: 1; 545 }; 546 547 struct btc_btinfo_hb2 { 548 u8 pan_active: 1; 549 u8 afh_update: 1; 550 u8 a2dp_active: 1; 551 u8 slave: 1; 552 u8 hid_slot: 2; 553 u8 hid_cnt: 2; 554 }; 555 556 struct btc_btinfo_hb3 { 557 u8 a2dp_bitpool: 6; 558 u8 tx_3M: 1; 559 u8 a2dp_sink: 1; 560 }; 561 562 union btc_btinfo { 563 u8 val; 564 struct btc_btinfo_lb2 lb2; 565 struct btc_btinfo_lb3 lb3; 566 struct btc_btinfo_hb0 hb0; 567 struct btc_btinfo_hb1 hb1; 568 struct btc_btinfo_hb2 hb2; 569 struct btc_btinfo_hb3 hb3; 570 }; 571 572 enum btc_rinfo_lo_b2 { 573 BTC_RINFO_INQPAG = BIT(2), 574 }; 575 576 enum btc_bt_hfp_type { 577 BTC_HFP_SCO = 0, 578 BTC_HFP_ESCO = 1, 579 BTC_HFP_ESCO_2SLOT = 2, 580 }; 581 582 enum btc_bt_hid_type { 583 BTC_HID_218 = BIT(0), 584 BTC_HID_418 = BIT(1), 585 BTC_HID_BLE = BIT(2), 586 BTC_HID_RCU = BIT(3), 587 BTC_HID_RCU_VOICE = BIT(4), 588 BTC_HID_OTHER_LEGACY = BIT(5) 589 }; 590 591 enum btc_bt_a2dp_type { 592 BTC_A2DP_LEGACY = 0, 593 BTC_A2DP_TWS_SNIFF = 1, /* Airpod */ 594 BTC_A2DP_TWS_RELAY = 2, /* RTL8763B */ 595 }; 596 597 enum btc_bt_PAN_type { 598 BTC_BT_PAN_ONLY = 0, 599 BTC_BT_OPP_ONLY = 1 600 }; 601 602 enum btc_bt_scan_type { 603 BTC_SCAN_INQ = 0, 604 BTC_SCAN_PAGE, 605 BTC_SCAN_BLE, 606 BTC_SCAN_INIT, 607 BTC_SCAN_TV, 608 BTC_SCAN_ADV, 609 BTC_SCAN_MAX1 610 }; 611 612 enum btc_bt_mailbox_id { 613 BTC_BTINFO_REPLY = 0x23, 614 BTC_BTINFO_AUTO = 0x27 615 }; 616 617 enum { 618 BTC_BT_HFP = BIT(0), 619 BTC_BT_HID = BIT(1), 620 BTC_BT_A2DP = BIT(2), 621 BTC_BT_PAN = BIT(3), 622 BTC_PROFILE_MAX = 4 623 }; 624 625 enum { 626 BTC_BT_IQK_OK = 0, 627 BTC_BT_IQK_START = 1, 628 BTC_BT_IQK_STOP = 2, 629 BTC_BT_IQK_MAX 630 }; 631 632 enum { 633 BTC_ANT_SHARED = 0, 634 BTC_ANT_DEDICATED, 635 BTC_ANTTYPE_MAX 636 }; 637 638 enum { 639 BTC_BT_ALONE = 0, 640 BTC_BT_BTG 641 }; 642 643 enum { 644 BTC_SWITCH_INTERNAL = 0, 645 BTC_SWITCH_EXTERNAL 646 }; 647 648 enum { 649 BTC_RESET_CX = BIT(0), 650 BTC_RESET_DM = BIT(1), 651 BTC_RESET_CTRL = BIT(2), 652 BTC_RESET_CXDM = BIT(0) | BIT(1), 653 BTC_RESET_BTINFO = BIT(3), 654 BTC_RESET_MDINFO = BIT(4), 655 BTC_RESET_ALL = 0xff 656 }; 657 658 enum btc_gnt_state { 659 BTC_GNT_HW = 0, 660 BTC_GNT_SW_LO, 661 BTC_GNT_SW_HI, 662 BTC_GNT_MAX 663 }; 664 665 enum btc_wl_max_tx_time { 666 BTC_MAX_TX_TIME_L1 = 500, 667 BTC_MAX_TX_TIME_L2 = 1000, 668 BTC_MAX_TX_TIME_L3 = 2000, 669 BTC_MAX_TX_TIME_DEF = 5280 670 }; 671 672 enum btc_wl_max_tx_retry { 673 BTC_MAX_TX_RETRY_L1 = 7, 674 BTC_MAX_TX_RETRY_L2 = 15, 675 BTC_MAX_TX_RETRY_DEF = 31 676 }; 677 678 struct btc_wl_tx_limit_para { 679 u8 en; 680 u8 tx_1ss; 681 u32 tx_time; /* unit: us */ 682 u16 tx_retry; 683 }; 684 685 struct btc_rf_trx_para { 686 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 687 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 688 u32 bt_tx_power; /* decrease Tx power (dB) */ 689 u32 bt_rx_gain; /* LNA constrain level */ 690 }; 691 692 struct btc_gnt_ctrl { 693 u8 gnt_bt_sw_en; 694 u8 gnt_bt; 695 u8 gnt_wl_sw_en; 696 u8 gnt_wl; 697 }; 698 699 struct btc_fw_dm { 700 u32 freerun: 1; 701 u32 wl_ps_ctrl: 2; /* 0: off, 1: force on, 2:forec off */ 702 u32 wl_mimo_ps: 1; 703 u32 leak_ap: 1; 704 u32 igno_bt: 1; 705 u32 noisy_level: 3; 706 u32 set_ant_path: 16; 707 u32 rsvd: 7; 708 }; 709 710 struct btc_cxr_result { 711 struct btc_fw_dm dm; 712 struct btc_rf_trx_para rf_trx_para; 713 u32 cx_state_map; 714 u32 policy_type; 715 u32 run_cnt; 716 717 char run_reason[BTC_RSN_MAXLEN]; 718 char run_action[BTC_ACT_MAXLEN]; 719 }; 720 721 struct btc_bt_hfp_desc { 722 u32 exist: 1; 723 u32 type: 2; /* refer to btc_bt_hfp_type */ 724 u32 rsvd: 29; 725 }; 726 727 struct btc_bt_hid_desc { 728 u32 exist: 1; 729 u32 slot_info: 2; 730 u32 pair_cnt: 2; 731 u32 type: 8; /* refer to btc_bt_hid_type */ 732 u32 rsvd: 19; 733 }; 734 735 struct btc_bt_a2dp_desc { 736 u8 exist: 1; 737 u8 exist_last: 1; 738 u8 play_latency: 1; 739 u8 type: 3; /* refer to btc_bt_a2dp_type */ 740 u8 active: 1; 741 u8 sink: 1; 742 743 u8 bitpool; 744 u16 vendor_id; 745 u32 device_name; 746 u32 flush_time; 747 }; 748 749 struct btc_bt_pan_desc { 750 u32 exist: 1; 751 u32 type: 1; /* refer to btc_bt_pan_type */ 752 u32 active: 1; 753 u32 rsvd: 29; 754 }; 755 756 struct btc_wl_nhm { 757 s8 instant_wl_nhm_dbm; 758 s8 instant_wl_nhm_per_mhz; 759 u16 valid_record_times; 760 s8 record_pwr[16]; 761 u8 record_ratio[16]; 762 s8 pwr; /* dbm_per_MHz */ 763 u8 ratio; 764 u8 current_status; 765 u8 refresh; 766 bool start_flag; 767 u8 last_ccx_rpt_stamp; 768 }; 769 770 struct btc_chip_ops { 771 void (*set_rfe)(struct btc_t *btc); 772 void (*init_cfg)(struct btc_t *btc); 773 void (*wl_pri)(struct btc_t *btc, u8 mask, bool state); 774 void (*wl_tx_power)(struct btc_t *btc, u32 level); 775 void (*wl_rx_gain)(struct btc_t *btc, u32 level); 776 void (*wl_s1_standby)(struct btc_t *btc, u32 state); 777 void (*wl_req_mac)(struct btc_t *btc, u8 mac_id); 778 void (*update_bt_cnt)(struct btc_t *btc); 779 u8 (*bt_rssi)(struct btc_t *btc, u8 val); 780 }; 781 782 struct btc_chip { 783 u8 chip_id; 784 u32 para_ver; /* chip parameter version */ 785 u8 btcx_desired; /* bt fw desired coex version */ 786 u32 wlcx_desired; /* wl fw desired coex version */ 787 u8 scbd; /* scoreboard version, 0: not support*/ 788 u8 mailbox; /* mailbox version, 0: not support */ 789 u8 pta_mode; 790 u8 pta_direction; 791 u8 afh_guard_ch; 792 const u8 *wl_rssi_thres; /* wl rssi thre level */ 793 const u8 *bt_rssi_thres; /* bt rssi thre level */ 794 u8 rssi_tol; /* rssi tolerance */ 795 struct btc_chip_ops *ops; 796 u8 mon_reg_num; 797 struct fbtc_mreg *mon_reg; 798 u8 rf_para_ulink_num; 799 struct btc_rf_trx_para *rf_para_ulink; 800 u8 rf_para_dlink_num; 801 struct btc_rf_trx_para *rf_para_dlink; 802 803 }; 804 805 struct btc_bt_scan_info { 806 u16 win; 807 u16 intvl; 808 u32 enable: 1; 809 u32 interlace: 1; 810 u32 rsvd: 30; 811 }; 812 813 struct btc_bt_rfk_info { 814 u32 run: 1; 815 u32 req: 1; 816 u32 timeout: 1; 817 u32 rsvd: 29; 818 }; 819 820 union btc_bt_rfk_info_map { 821 u32 val; 822 struct btc_bt_rfk_info map; 823 }; 824 825 struct btc_bt_ver_info { 826 u32 fw_coex; /* match with which coex_ver */ 827 u32 fw; 828 }; 829 struct btc_bool_sta_chg { /* status change varible */ 830 u32 now: 1; 831 u32 last: 1; 832 u32 remain: 1; 833 u32 srvd: 29; 834 }; 835 836 struct btc_u8_sta_chg { /* status change varible */ 837 u8 now; 838 u8 last; 839 u8 remain; 840 u8 rsvd; 841 }; 842 843 struct btc_bit_remap { 844 u32 index; 845 u32 bpos; 846 }; 847 848 struct btc_ant_info { 849 u8 type; /* shared, dedicated */ 850 u8 num; 851 u8 isolation; 852 853 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 854 u8 diversity: 1; 855 }; 856 857 struct btc_traffic { 858 enum rtw_tfc_lvl tx_lvl; 859 enum rtw_tfc_sts tx_sts; 860 enum rtw_tfc_lvl rx_lvl; 861 enum rtw_tfc_sts rx_sts; 862 u16 tx_rate; 863 u16 rx_rate; 864 u8 tx_1ss_limit; 865 }; 866 867 struct btc_wl_scan_info { 868 u8 band[HW_PHY_MAX]; 869 u8 phy_map; 870 u8 rsvd; 871 }; 872 873 struct btc_wl_dbcc_info { 874 u8 op_band[HW_PHY_MAX]; /* op band in each phy */ 875 u8 scan_band[HW_PHY_MAX]; /* scan band in each phy */ 876 u8 real_band[HW_PHY_MAX]; 877 u8 role[HW_PHY_MAX]; /* role in each phy */ 878 }; 879 880 struct btc_wl_active_role { /* struct size must be n*4 bytes */ 881 u8 connected: 1; 882 u8 pid: 3; 883 u8 phy: 1; 884 u8 noa: 1; 885 u8 band: 2; /* enum band_type RF band: 2.4G/5G/6G */ 886 887 u8 client_ps: 1; 888 u8 bw: 7; /* enum channel_width */ 889 890 u8 role; /*enum role_type */ 891 u8 ch; 892 893 u16 tx_lvl; 894 u16 rx_lvl; 895 u16 tx_rate; 896 u16 rx_rate; 897 898 u32 noa_duration; /* ms */ 899 }; 900 901 struct btc_wl_role_info_bpos { 902 u16 none: 1; 903 u16 station: 1; 904 u16 ap: 1; 905 u16 vap: 1; 906 u16 adhoc: 1; 907 u16 adhoc_master: 1; 908 u16 mesh: 1; 909 u16 moniter: 1; 910 u16 p2p_device: 1; 911 u16 p2p_gc: 1; 912 u16 p2p_go: 1; 913 u16 nan: 1; 914 }; 915 916 union btc_wl_role_info_map { 917 u16 val; 918 struct btc_wl_role_info_bpos role; 919 }; 920 921 struct btc_wl_scc_ctrl { 922 u8 null_role1; 923 u8 null_role2; 924 u8 ebt_null; /* if tx null at EBT slot */ 925 u8 rsvd; 926 }; 927 928 struct btc_wl_role_info { /* struct size must be n*4 bytes */ 929 u8 connect_cnt; 930 u8 link_mode; 931 union btc_wl_role_info_map role_map; 932 struct btc_wl_active_role active_role[MAX_WIFI_ROLE_NUMBER]; 933 u32 mrole_type; /* btc_wl_mrole_type */ 934 u32 mrole_noa_duration; /* ms */ 935 }; 936 937 struct btc_statistic { 938 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 939 struct btc_traffic traffic; 940 }; 941 942 struct btc_wl_stat_info { 943 u8 pid; 944 struct btc_statistic stat; 945 }; 946 947 struct btc_wl_link_info { 948 struct btc_statistic stat; 949 enum rtw_traffic_dir dir; 950 struct rtw_chan_def chdef; 951 952 u8 mode; /* wl mode: 11b, 11g, 11n... */ 953 u8 ch; 954 u8 bw; 955 u8 band; /* enum RF band: 2.4G/5G/6G */ 956 u8 role; /*enum role_type */ 957 u8 pid; /* MAC HW Port id: 0~4 */ 958 u8 phy; /* PHY-0 or PHY-1*/ 959 u8 dtim_period; 960 961 u8 busy; 962 u8 rssi_state[BTC_WL_RSSI_THMAX]; 963 u8 mac_addr[6]; 964 u8 tx_retry; 965 966 u16 mac_id; /* 0~63 */ 967 968 u32 bcn_period; 969 u32 noa_duration; /* us */ 970 u32 busy_t; /* busy start time */ 971 u32 tx_time; /* the original max_tx_time */ 972 u32 client_cnt; /* connected-client cnt for p2p-GO/soft-AP mode */ 973 u32 rx_rate_drop_cnt; 974 975 u32 active: 1; 976 u32 noa: 1; /* Todo: for P2P */ 977 u32 client_ps: 1; /* Todo: for soft-AP */ 978 u32 connected: 2; 979 u32 stbc_ht_tx:1; 980 u32 stbc_vht_tx:1; 981 u32 stbc_he_tx:1; 982 }; 983 984 struct btc_wl_rfk_info { 985 u32 state: 2; 986 u32 path_map: 4; 987 u32 phy_map: 2; 988 u32 band: 2; /*0:2g, 1:5g, 2:6g */ 989 u32 type: 8; 990 u32 rsvd: 14; 991 }; 992 993 struct btc_wl_ver_info { 994 u32 fw_coex; /* match with which coex_ver */ 995 u32 fw; 996 u32 mac; 997 u32 bb; 998 u32 rf; 999 }; 1000 1001 struct btc_wl_afh_info { 1002 u8 en; 1003 u8 ch; 1004 u8 bw; 1005 u8 rsvd; 1006 }; 1007 1008 struct btc_ops { 1009 void (*fw_cmd)(struct btc_t *btc, u8 h2c_class, u8 h2c_func, 1010 u8 *param, u16 len); 1011 void (*ntfy_power_on)(struct btc_t *btc); 1012 void (*ntfy_power_off)(struct btc_t *btc); 1013 void (*ntfy_init_coex)(struct btc_t *btc, u8 mode); 1014 void (*ntfy_scan_start)(struct btc_t *btc, u8 band_idx, u8 band); 1015 void (*ntfy_scan_finish)(struct btc_t *btc, u8 band_idx); 1016 void (*ntfy_switch_band)(struct btc_t *btc, u8 band_idx, u8 band); 1017 void (*ntfy_specific_packet)(struct btc_t *btc, u8 pkt_type); 1018 void (*ntfy_role_info)(struct btc_t *btc, u8 rid, 1019 struct rtw_wifi_role_t *wrole, 1020 struct rtw_phl_stainfo_t *sta, 1021 enum role_state reason); 1022 void (*ntfy_radio_state)(struct btc_t *btc, u8 rf_state); 1023 void (*ntfy_customerize)(struct btc_t *btc, u8 type, u16 len, u8 *buf); 1024 u8 (*ntfy_wl_rfk)(struct btc_t *btc, u8 phy, u8 type, u8 state); 1025 void (*ntfy_wl_sta)(struct btc_t *btc, struct rtw_stats *phl_stats, 1026 u8 ntfy_num, struct rtw_phl_stainfo_t *sta[], 1027 u8 reason); 1028 void (*ntfy_fwinfo)(struct btc_t *btc, u8 *buf, u32 len, u8 cls, 1029 u8 func); 1030 void (*ntfy_timer)(struct btc_t *btc, u16 tmr_id); 1031 }; 1032 1033 struct btc_bt_smap { 1034 u32 connect: 1; 1035 u32 ble_connect: 1; 1036 u32 acl_busy: 1; 1037 u32 sco_busy: 1; 1038 u32 mesh_busy: 1; 1039 u32 inq_pag: 1; 1040 }; 1041 1042 union btc_bt_state_map { 1043 u32 val; 1044 struct btc_bt_smap map; 1045 }; 1046 1047 struct btc_bt_link_info { 1048 struct btc_u8_sta_chg profile_cnt; 1049 struct btc_bool_sta_chg multi_link; 1050 struct btc_bool_sta_chg relink; 1051 struct btc_bt_hfp_desc hfp_desc; 1052 struct btc_bt_hid_desc hid_desc; 1053 struct btc_bt_a2dp_desc a2dp_desc; 1054 struct btc_bt_pan_desc pan_desc; 1055 union btc_bt_state_map status; 1056 1057 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1058 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1059 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1060 u8 afh_map[12]; 1061 1062 u32 role_sw: 1; 1063 u32 slave_role: 1; 1064 u32 afh_update: 1; 1065 u32 cqddr: 1; 1066 u32 rssi: 8; 1067 u32 tx_3M: 1; 1068 u32 rsvd: 19; 1069 }; 1070 1071 struct btc_3rdcx_info { 1072 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1073 u8 hw_coex; 1074 u16 rsvd; 1075 }; 1076 1077 struct btc_rf_para { 1078 u32 tx_pwr_freerun; 1079 u32 rx_gain_freerun; 1080 u32 tx_pwr_perpkt; 1081 u32 rx_gain_perpkt; 1082 }; 1083 1084 struct btc_bt_info { 1085 struct btc_bt_link_info link_info; 1086 struct btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; 1087 struct btc_bt_ver_info ver_info; 1088 struct btc_bool_sta_chg enable; 1089 struct btc_bool_sta_chg inq_pag; 1090 struct btc_rf_para rf_para; /* for record */ 1091 union btc_bt_rfk_info_map rfk_info; 1092 1093 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1094 1095 u32 scbd; /* scoreboard value */ 1096 u32 feature; 1097 1098 u32 mbx_avl: 1; /* mailbox available */ 1099 u32 whql_test: 1; 1100 u32 igno_wl: 1; 1101 u32 reinit: 1; 1102 u32 ble_scan_en: 1; 1103 u32 btg_type: 1; /* BT located at BT only or BTG */ 1104 u32 inq: 1; 1105 u32 pag: 1; 1106 1107 u32 run_patch_code: 1; 1108 u32 hi_lna_rx: 1; 1109 u32 scan_rx_low_pri: 1; 1110 1111 u32 rsvd: 21; 1112 }; 1113 1114 struct btc_wl_smap { 1115 u32 busy: 1; 1116 u32 scan: 1; 1117 u32 connecting: 1; 1118 u32 roaming: 1; 1119 u32 _4way: 1; 1120 u32 rf_off: 1; 1121 u32 lps: 2; /* 1: LPS-Protocol + WL_power, 2:LPS_Protocol */ 1122 u32 ips: 1; 1123 u32 init_ok: 1; 1124 u32 traffic_dir : 2; 1125 u32 rf_off_pre: 1; 1126 u32 lps_pre: 2; 1127 }; 1128 1129 union btc_wl_state_map { 1130 u32 val; 1131 struct btc_wl_smap map; 1132 }; 1133 1134 struct btc_dm_emap { 1135 u32 init: 1; 1136 u32 pta_owner: 1; 1137 u32 wl_rfk_timeout: 1; 1138 u32 bt_rfk_timeout: 1; 1139 1140 u32 wl_fw_hang: 1; 1141 u32 offload_mismatch: 1; 1142 u32 cycle_hang: 1; 1143 u32 w1_hang: 1; 1144 1145 u32 b1_hang: 1; 1146 u32 tdma_no_sync: 1; 1147 u32 wl_slot_drift: 1; 1148 u32 bt_slot_drift: 1; /* for external slot control */ 1149 }; 1150 1151 union btc_dm_error_map { 1152 u32 val; 1153 struct btc_dm_emap map; 1154 }; 1155 1156 struct btc_wl_info { 1157 struct btc_wl_link_info link_info[MAX_WIFI_ROLE_NUMBER]; 1158 struct btc_wl_rfk_info rfk_info; 1159 struct btc_wl_ver_info ver_info; 1160 struct btc_wl_afh_info afh_info; 1161 struct btc_wl_role_info role_info; 1162 struct btc_wl_scan_info scan_info; 1163 struct btc_wl_dbcc_info dbcc_info; 1164 struct btc_bool_sta_chg cck_lock; 1165 struct btc_rf_para rf_para; /* for record */ 1166 union btc_wl_state_map status; 1167 struct btc_wl_nhm nhm; 1168 1169 u8 iot_peer; 1170 u8 rssi_level;/* the overall-role rssi-level 0~4, "low_rssi->hi_level"*/ 1171 u8 bssid[6]; 1172 u8 pta_req_mac; 1173 u8 bt_polut_type[2]; /* BT polluted WL-Tx type for phy0/1 */ 1174 1175 u32 scbd; 1176 }; 1177 1178 struct btc_module { 1179 struct btc_ant_info ant; 1180 u8 rfe_type; 1181 u8 kt_ver; 1182 1183 u8 bt_solo: 1; 1184 u8 bt_pos: 1; /* wl-end view: get from efuse, must compare bt.btg_type */ 1185 u8 switch_type: 1; /* WL/BT switch type: 0: internal, 1: external */ 1186 1187 u8 rsvd; 1188 }; 1189 1190 struct btc_init_info { 1191 struct btc_module module; 1192 u8 wl_guard_ch; 1193 1194 u8 wl_only: 1; 1195 u8 wl_init_ok: 1; 1196 u8 dbcc_en: 1; 1197 u8 cx_other: 1; 1198 u8 bt_only: 1; 1199 1200 u16 rsvd; 1201 }; 1202 1203 /* recird the last 20 reason/action */ 1204 struct btc_dm_step { 1205 char step[BTC_DM_MAXSTEP][BTC_RSN_MAXLEN]; 1206 u32 cnt; 1207 }; 1208 1209 /* dynamic coex mechanism */ 1210 struct btc_dm { 1211 struct fbtc_slot slot[CXST_MAX]; 1212 struct fbtc_slot slot_now[CXST_MAX]; 1213 struct fbtc_tdma tdma; 1214 struct fbtc_tdma tdma_now; 1215 struct btc_gnt_ctrl gnt[2]; 1216 struct btc_init_info init_info; /* pass to wl_fw if offload */ 1217 struct btc_rf_trx_para rf_trx_para; 1218 struct btc_wl_tx_limit_para wl_tx_limit; 1219 struct btc_wl_scc_ctrl wl_scc; 1220 struct btc_dm_step dm_step; 1221 union btc_dm_error_map error; 1222 1223 char run_reason[BTC_RSN_MAXLEN]; 1224 char run_action[BTC_ACT_MAXLEN]; 1225 1226 u16 slot_dur[CXST_MAX]; /* for user-define slot duration */ 1227 1228 u32 set_ant_path; 1229 u32 cnt_dm[BTC_DCNT_MAX]; 1230 u32 cnt_notify[BTC_NCNT_MAX]; 1231 1232 u32 wl_only: 1; /* drv->Fw if offload */ 1233 u32 wl_fw_cx_offload: 1; /* BTC_CX_FW_OFFLOAD from FW code */ 1234 u32 freerun: 1; 1235 u32 wl_ps_ctrl: 2; /* 0: off, 1: force on, 2:forec off */ 1236 u32 wl_mimo_ps: 1; 1237 u32 leak_ap: 1; 1238 u32 noisy_level: 3; 1239 u32 coex_info_map: 8; 1240 u32 bt_only: 1; /* drv->Fw if offload */ 1241 u32 wl_btg_rx: 1; /* if wl rx shared with bt */ 1242 u32 trx_para_level: 8; /* trx parameter level */ 1243 u32 wl_stb_chg: 1; /* if change s1 WL standby mode table = Rx */ 1244 u32 rsvd: 3; 1245 }; 1246 1247 /* the wl/bt/zb cx instance */ 1248 struct btc_cx { 1249 struct btc_wl_info wl; 1250 struct btc_bt_info bt; 1251 struct btc_3rdcx_info other; 1252 struct btc_rf_trx_para rf_para; 1253 u32 state_map; /* wl/bt combined state map */ 1254 u32 cnt_bt[BTC_BCNT_MAX]; 1255 u32 cnt_wl[BTC_WCNT_MAX]; 1256 }; 1257 1258 struct btc_ctrl { 1259 u32 manual: 1; 1260 u32 igno_bt: 1; 1261 u32 always_freerun: 1; 1262 u32 rsvd: 29; 1263 }; 1264 1265 struct btc_dbg { 1266 /* cmd "rb" */ 1267 bool rb_done; 1268 u32 rb_val; 1269 }; 1270 1271 struct btc_tmr { 1272 void *btc; 1273 u16 id; 1274 _os_timer tmr; 1275 }; 1276 1277 struct btc_t { 1278 struct rtw_phl_com_t *phl; 1279 struct rtw_hal_com_t *hal; 1280 1281 struct btc_ops *ops; 1282 const struct btc_chip *chip; 1283 1284 struct btc_cx cx; 1285 struct btc_dm dm; 1286 struct btc_ctrl ctrl; 1287 struct btc_module mdinfo; 1288 struct btf_fwinfo fwinfo; 1289 struct btc_dbg dbg; 1290 1291 /* btc timers */ 1292 bool tmr_init; 1293 bool tmr_stop; 1294 struct btc_tmr timer[BTC_TIMER_MAX]; 1295 _os_timer delay_tmr; /* a delayed timer to start periodic timer (wait phl started) */ 1296 1297 char mbuf[BTC_MSG_MAXLEN]; /* msg buffer */ 1298 size_t mlen; /* max msg len */ 1299 1300 u8 policy[BTC_POLICY_MAXLEN]; /* coex policy buffer */ 1301 u16 policy_len; 1302 u16 policy_type; 1303 1304 u8 hubmsg[BTC_HUBMSG_MAXLEN]; /* phl hub msg */ 1305 u16 hubmsg_len; 1306 u32 hubmsg_cnt; 1307 u32 bt_req_len; /* request bt-slot in WL SCC/MCC +BT coex */ 1308 bool bt_req_en; 1309 }; 1310 1311 static void _send_fw_cmd(struct btc_t *btc, u8 h2c_class, u8 h2c_func, 1312 u8 *param, u16 len); 1313 static void _ntfy_power_on(struct btc_t *btc); 1314 static void _ntfy_power_off(struct btc_t *btc); 1315 static void _ntfy_init_coex(struct btc_t *btc, u8 mode); 1316 static void _ntfy_scan_start(struct btc_t *btc, u8 phy_idx, u8 band); 1317 static void _ntfy_scan_finish(struct btc_t *btc, u8 pyh_idx); 1318 static void _ntfy_switch_band(struct btc_t *btc, u8 phy_idx, u8 band); 1319 static void _ntfy_specific_packet(struct btc_t *btc, u8 pkt_type); 1320 static void _ntfy_role_info(struct btc_t *btc, u8 rid, 1321 struct rtw_wifi_role_t *wrole, 1322 struct rtw_phl_stainfo_t *sta, 1323 enum role_state reason); 1324 static void _ntfy_radio_state(struct btc_t *btc, u8 rf_state); 1325 static void _ntfy_customerize(struct btc_t *btc, u8 type, u16 len, u8 *buf); 1326 static u8 _ntfy_wl_rfk(struct btc_t *btc, u8 phy_path, u8 type, u8 state); 1327 static void _ntfy_wl_sta(struct btc_t *btc, struct rtw_stats *phl_stats, 1328 u8 ntfy_num, struct rtw_phl_stainfo_t *sta[], 1329 u8 reason); 1330 static void _ntfy_fwinfo(struct btc_t *btc, u8 *buf, u32 len, u8 cls, u8 func); 1331 static void _ntfy_timer(struct btc_t *btc, u16 tmr_id); 1332 1333 #ifdef BTC_8852A_SUPPORT 1334 extern const struct btc_chip chip_8852a; 1335 #endif 1336 #ifdef BTC_8852B_SUPPORT 1337 extern const struct btc_chip chip_8852b; 1338 #endif 1339 #ifdef BTC_8852C_SUPPORT 1340 extern const struct btc_chip chip_8852c; 1341 #endif 1342 extern const u32 coex_ver; 1343 1344 void _update_bt_scbd(struct btc_t *btc, bool only_update); 1345 bool hal_btc_init(struct btc_t *btc); 1346 void hal_btc_deinit(struct btc_t *btc); 1347 u32 _read_cx_reg(struct btc_t *btc, u32 offset); 1348 u8 _read_cx_ctrl(struct btc_t *btc); 1349 void _write_bt_reg(struct btc_t *btc, u8 reg_type, u16 addr, u32 val); 1350 void _read_bt_reg(struct btc_t *btc, u8 reg_type, u16 addr); 1351 u32 _read_scbd(struct btc_t *btc); 1352 void _write_scbd(struct btc_t *btc, u32 val, bool state); 1353 void _run_coex(struct btc_t *btc, const char *reason); 1354 void _set_init_info(struct btc_t *btc); 1355 void _set_bt_psd_report(struct btc_t *btc, u8 start_idx, u8 rpt_type); 1356 void _update_dm_step(struct btc_t *btc, const char *strin); 1357 void hal_btc_send_event(struct btc_t *btc, u8 *buf, u32 len, u16 ev_id); 1358 u8 _get_wl_role_idx(struct btc_t *btc, u8 role); 1359 #endif /*_HAL_BTC_H_*/ 1360