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/optee_os/lib/libmbedtls/mbedtls/include/mbedtls/
H A Dssl_cache.h4 * \brief SSL session cache implementation
35 #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /*!< Maximum entries in cache */
48 * \brief This structure is used for storing cache entries
65 * \brief Cache context
69 int MBEDTLS_PRIVATE(timeout); /*!< cache entry timeout */
77 * \brief Initialize an SSL cache context
79 * \param cache SSL cache context
81 void mbedtls_ssl_cache_init(mbedtls_ssl_cache_context *cache);
84 * \brief Cache get callback implementation
87 * \param data The SSL cache context to use.
[all …]
/optee_os/lib/libmbedtls/mbedtls/library/
H A Dssl_cache.c2 * SSL session cache implementation
24 void mbedtls_ssl_cache_init(mbedtls_ssl_cache_context *cache) in mbedtls_ssl_cache_init() argument
26 memset(cache, 0, sizeof(mbedtls_ssl_cache_context)); in mbedtls_ssl_cache_init()
28 cache->timeout = MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT; in mbedtls_ssl_cache_init()
29 cache->max_entries = MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES; in mbedtls_ssl_cache_init()
32 mbedtls_mutex_init(&cache->mutex); in mbedtls_ssl_cache_init()
37 static int ssl_cache_find_entry(mbedtls_ssl_cache_context *cache, in ssl_cache_find_entry() argument
48 for (cur = cache->chain; cur != NULL; cur = cur->next) { in ssl_cache_find_entry()
50 if (cache->timeout != 0 && in ssl_cache_find_entry()
51 (int) (t - cur->timestamp) > cache->timeout) { in ssl_cache_find_entry()
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/optee_os/core/arch/arm/dts/
H A Dfsl-lx2160a.dtsi33 d-cache-size = <0x8000>;
34 d-cache-line-size = <64>;
35 d-cache-sets = <128>;
36 i-cache-size = <0xC000>;
37 i-cache-line-size = <64>;
38 i-cache-sets = <192>;
39 next-level-cache = <&cluster0_l2>;
50 d-cache-size = <0x8000>;
51 d-cache-line-size = <64>;
52 d-cache-sets = <128>;
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/optee_os/core/arch/arm/kernel/
H A Dcache_helpers_a32.S14 * Cache line size helpers
31 * This macro can be used for implementing various data cache operations `op`
85 * Data cache operations by set/way to the level specified
90 * r1: The cache level to begin operation from
92 * r3: The last cache level to operate on
93 * and will carry out the operation on each data cache from level 0
97 * clidr_el1 cache information before invoking the main function
111 adr r11, dcsw_loop_table // compute cache op based on the operation type
112 add r6, r11, r0, lsl #3 // cache op is 2x32-bit instructions
114 add r10, r1, r1, LSR #1 // Work out 3x current cache level
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H A Dcache_helpers_a64.S26 * This macro can be used for implementing various data cache operations `op`
78 * Data cache operations by set/way to the level specified
82 * x3: The last cache level to operate on
84 * x10: The cache level to begin operation from
85 * and will carry out the operation on each data cache from level 0
89 * clidr_el1 cache information before invoking the main function
109 add x2, x10, x10, lsr #1 // work out 3x current cache level
110 lsr x1, x0, x2 // extract cache type bits from clidr
111 and x1, x1, #7 // mask the bits for current cache only
112 cmp x1, #2 // see what cache we have at this level
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H A Darm32_sysreg.txt13 CCSIDR c0 1 c0 0 RO Cache Size ID Registers
14 CLIDR c0 1 c0 1 RO Cache Level ID Register
15 CSSELR c0 2 c0 0 RW Cache Size Selection Register
16 CTR c0 0 c0 1 RO Cache Type Register
66 @ B3.18.6 Cache maintenance operations, functional group, VMSA
70 DCCIMVAC c7 0 c14 1 WO Data cache clean and invalidate by MVA PoC
71 DCCISW c7 0 c14 2 WO Data cache clean and invalidate by set/way
72 DCCMVAC c7 0 c10 1 WO Data cache clean by MVA PoC
73 DCCMVAU c7 0 c11 1 WO Data cache clean by MVA PoU
74 DCCSW c7 0 c10 2 WO Data cache clean by set/way
[all …]
H A Dtz_ssvce_pl310_a32.S51 * clean & invalidate the whole L2 cache.
58 /* Wait for all cache ways to be cleaned and invalidated */
65 /* Cache Sync */
68 * Wait for writing cache sync
69 * To PL310, Cache sync is atomic opertion, no need to check
200 * clean L2 cache by physical address range.
209 * invalidate L2 cache by physical address range.
218 * clean and invalidate L2 cache by physical address range.
/optee_os/lib/libutee/include/
H A Dtee_internal_api_extensions.h22 * Cache maintenance support (TA requires the CACHE_MAINTENANCE property)
24 * TEE_CacheClean() Write back to memory any dirty data cache lines. The line
27 * TEE_CacheFlush() Purges any valid data cache lines. Any dirty cache lines
28 * are first written back to memory, then the cache line is
31 * TEE_CacheInvalidate() Invalidate any valid data cache lines. Any dirty line
/optee_os/.github/workflows/
H A Dci.yml344 - name: Generate cache key
347 echo "CACHE_KEY=builds-cache-${HASH}-${GITHUB_SHA}" >> ${GITHUB_ENV}
348 echo "CACHE_RESTORE_KEY=builds-cache-${HASH}" >> ${GITHUB_ENV}
349 - name: Restore build cache
350 uses: actions/cache@v4
352 path: /github/home/.cache/ccache
433 - name: Generate cache key
436 echo "CACHE_KEY=qemuv7_check-cache-${HASH}-${GITHUB_SHA}" >> $GITHUB_ENV
437 echo "CACHE_RESTORE_KEY=qemuv7_check-cache-${HASH}" >> ${GITHUB_ENV}
438 - name: Restore build cache
[all...]
/optee_os/core/arch/arm/include/kernel/
H A Dtz_proc_def.h62 * CP15 Cache register
79 * CP15 cache lockdown register
87 * CP15 cache cleaning constant definition
91 /* Warning: this assumes a 256 lines/way cache (32kB cache) */
/optee_os/core/drivers/
H A Datmel_shdwc_a32.S18 * Code size of shutdown assembly must fit in a single Cortex-A5 cache
24 .error "Shutdown assembly code exceeds cache line size"
31 * This function is in assembly to be sure the code fits in a single cache line.
55 /* Align to cache line to ensure the rest of code fits in a single line */
/optee_os/core/include/kernel/
H A Dtee_misc.h53 * Allocate maximum cache line aligned memory buffer.
55 * Both size and base address of the memory buffer will be maximum cache line
56 * aligned to make it safe to perform cache maintenance operations over the
59 * This is needed when non-cache coherent peripherals are used and memory area
H A Dcache_helpers.h14 /* Data Cache set/way op type defines */
37 * Get system maximum cache line size.
/optee_os/core/drivers/crypto/ele/include/
H A Dmemutils.h15 #include <tee/cache.h>
34 * Allocate cache aligned buffer, initialize it with 0's, copy data from
35 * @buf to newly allocated buffer and cache flush the buffer.
/optee_os/core/arch/arm/tee/
H A Dcache.c9 #include <tee/cache.h>
12 * tee_uta_cache_operation - dynamic cache clean/inval request from a TA.
16 * cache_op_inner(), and outer cache sync are part of cache_op_outer().
H A Dsvc_cache.c9 #include <tee/cache.h>
24 * TAs are allowed to operate cache maintenance on TA memref parameters in syscall_cache_operation()
/optee_os/core/drivers/crypto/versal/
H A Dipi.c13 #include <tee/cache.h>
97 goto cache; in versal_crypto_request()
100 goto cache; in versal_crypto_request()
105 cache: in versal_crypto_request()
/optee_os/core/arch/arm/plat-sam/
H A Dsam_pl310.c40 /* L2 Cache Controller (L2CC) */
42 #define L2CC_DCR_DCL BIT(0) /* Disable Cache Linefill */
66 /* invalidate all cache ways */ in arm_cl2_config()
/optee_os/core/arch/arm/plat-imx/
H A Dimx_pl310.c40 * The L2 cache controller(PL310) version on the i.MX6D/Q in arm_cl2_config()
42 * The L2 cache controller(PL310) version on the in arm_cl2_config()
63 /* invalidate all cache ways */ in arm_cl2_config()
H A Da7_plat_init.S38 * L1RADIS: L1 Data Cache read-allocate mode disable [bit12=0]
39 * L2RADIS: L2 Data Cache read-allocate mode disable [bit11=0]
/optee_os/core/arch/arm/plat-ti/
H A Dapi_monitor_index_a15.h20 /* Write the L2 Cache Controller Auxiliary Control */
24 /* L2 Cache Prefetch Control Register */
/optee_os/core/drivers/crypto/caam/utils/
H A Dutils_dmaobj.c17 #include <tee/cache.h>
303 * Apply the cache operation @op to the DMA Object (SGT or buffer)
305 * @op Cache operation
337 * Check if the buffer start/end addresses are aligned on the cache line.
339 * maximum length @maxlen to use is inside a cache line size. In this case,
377 * Length of the entry is not aligned on cache size in check_buffer_alignment()
380 DMAOBJ_TRACE("Length %zu vs cache line %u", in check_buffer_alignment()
401 * is not cache size aligned. in check_buffer_alignment()
404 DMAOBJ_TRACE("Rem length %zu vs cache line %u", in check_buffer_alignment()
412 * Insert a new entry to make buffer on a cache line. in check_buffer_alignment()
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/optee_os/core/arch/riscv/kernel/
H A Dcache_helpers_rv.S10 * On the below data cache management, we rely on FENCE instruction.
46 * fetches on the same hart. This implies instruction cache
/optee_os/core/drivers/crypto/caam/include/
H A Dcaam_utils_mem.h29 * Allocate memory aligned with a cache line and initialize it to 0's.
73 * Allocate internal driver buffer aligned with a cache line and initialize
82 * Allocate internal driver buffer aligned with a cache line.
/optee_os/core/arch/arm/mm/
H A Dcore_mmu.c107 * - Secure access: The data in the cache is only affected by the in cache_op_outer()
109 * - Non-secure access: The data in the cache is only affected by the in cache_op_outer()
112 …umentation/ddi0246/a/programmer-s-model/register-descriptions/register-7--cache-maintenance-operat… in cache_op_outer()
115 * base address to do physical address based cache operation on the in cache_op_outer()

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