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/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/hwcnt/
H A Dmali_kbase_hwcnt_gpu.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * (C) COPYRIGHT 2018, 2020-2022 ARM Limited. All rights reserved.
18 * http://www.gnu.org/licenses/gpl-2.0.html.
52 * enum kbase_hwcnt_gpu_group_type - GPU hardware counter group types, used to
61 * enum kbase_hwcnt_gpu_v5_block_type - GPU V5 hardware counter block types,
100 * enum kbase_hwcnt_set - GPU hardware counter sets
114 * struct kbase_hwcnt_physical_enable_map - Representation of enable map
139 * struct kbase_hwcnt_gpu_info - Information about hwcnt blocks on the GPUs.
154 * struct kbase_hwcnt_curr_config - Current Configuration of HW allocated to the
161 * re-partitioning (possible with partition manager). Thus, the HWC needs to be
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H A Dmali_kbase_hwcnt_types.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * (C) COPYRIGHT 2018, 2020-2022 ARM Limited. All rights reserved.
18 * http://www.gnu.org/licenses/gpl-2.0.html.
25 * dump buffers and enable maps within a system.
28 * enable maps.
58 * A catch-all term for block headers and block counters.
60 * Enable Map:
63 * Dump Buffer:
70 * same dump buffer layout as an MP4 GPU with a core mask of 0b1111. In this
75 * Structure describing the physical layout of the enable map and dump buffers
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/OK3568_Linux_fs/kernel/include/linux/usb/
H A Dr8a66597.h1 // SPDX-License-Identifier: GPL-2.0
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
138 #define XTAL 0xC000 /* b15-14: Crystal selection */
142 #define XCKE 0x2000 /* b13: External clock enable */
144 #define SCKE 0x0400 /* b10: USB clock enable */
147 #define HSE 0x0080 /* b7: Hi-speed enable */
149 #define DRPD 0x0020 /* b5: D+/- pull down control */
151 #define USBE 0x0001 /* b0: USB module operation enable */
154 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
155 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
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/OK3568_Linux_fs/kernel/drivers/media/platform/
H A Dvia-camera.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define VCR_IC_ACTBUF 0x0018 /* Active video buffer */
13 #define VCR_IC_INTEN 0x0100 /* End of active video int. enable */
14 #define VCR_IC_VBIINT 0x0200 /* End of VBI int enable */
15 #define VCR_IC_VBIBUF 0x0400 /* Current VBI buffer */
18 #define VCR_TSC_ENABLE 0x000001 /* Transport stream input enable */
20 #define VCR_TSC_METHOD 0x00000c /* DMA method (non-functional) */
22 #define VCR_TSC_CBMODE 0x080000 /* Change buffer by byte count */
28 #define VCR_CI_ENABLE 0x00000001 /* Capture enable */
31 #define VCR_CI_VIPEN 0x00000008 /* VIP enable */
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/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/csf/
H A Dmali_kbase_csf_trace_buffer.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * (C) COPYRIGHT 2018-2022 ARM Limited. All rights reserved.
18 * http://www.gnu.org/licenses/gpl-2.0.html.
35 * kbase_csf_firmware_trace_buffers_init - Initialize trace buffers
40 * - One memory page of GPU-readable, CPU-writable memory is used for
42 * - One memory page of GPU-writable, CPU-readable memory is used for
44 * - A data buffer of GPU-writable, CPU-readable memory is allocated
45 * for each trace buffer.
48 * insert, extract and data buffer variables. The size and the trace
49 * enable bits are not dereferenced by the GPU and shall be written
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
119 /* set interrupt mapping enable rx */
123 /* set interrupt mapping enable tx */
157 void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable);
167 /* set rx dca enable */
173 /* set rx descriptor data buffer size */
178 /* set rx descriptor dca enable */
182 /* set rx descriptor enable */
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/OK3568_Linux_fs/kernel/drivers/usb/renesas_usbhs/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-1.0+ */
100 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
101 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
102 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
103 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
107 #define SCKE (1 << 10) /* USB Module Clock Enable */
108 #define CNEN (1 << 8) /* Single-ended receiver operation Enable */
109 #define HSE (1 << 7) /* High-Speed Operation Enable */
111 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
113 #define USBE (1 << 0) /* USB Module Operation Enable */
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/OK3568_Linux_fs/kernel/drivers/media/rc/
H A Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
18 #define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */
24 #define ENE_FW1_ENABLE 0x01 /* enable fw processing */
26 #define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/
27 #define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/
30 #define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
31 #define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
32 #define ENE_FW1_IRQ 0x80 /* enable interrupt */
36 #define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */
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/OK3568_Linux_fs/kernel/drivers/media/platform/sti/delta/
H A Ddelta-mjpeg-fw.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * @display_luma_p: address of the luma buffer
17 * @display_chroma_p: address of the chroma buffer
31 * @display_luma_p: address of the luma buffer
32 * @display_chroma_p: address of the chroma buffer
33 * @display_decimated_luma_p: address of the decimated luma buffer
34 * @display_decimated_chroma_p: address of the decimated chroma buffer
49 /* enable decimated (for display) reconstruction */
51 /* enable main (for display) reconstruction */
53 /* enable both main & decimated (for display) reconstruction */
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/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/hwcnt/backend/
H A Dmali_kbase_hwcnt_backend_csf_if.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * (C) COPYRIGHT 2021-2022 ARM Limited. All rights reserved.
18 * http://www.gnu.org/licenses/gpl-2.0.html.
36 * struct kbase_hwcnt_backend_csf_if_enable - enable hardware counter collection
42 * @counter_set: The performance counter set to enable.
56 * struct kbase_hwcnt_backend_csf_if_prfcnt_info - Performance counter
59 * counters are sub-divided into 4 classes: front-end, shader, tiler, and
83 * typedef kbase_hwcnt_backend_csf_if_assert_lock_held_fn - Assert that the
86 * @ctx: Non-NULL pointer to a CSF context.
92 * typedef kbase_hwcnt_backend_csf_if_lock_fn - Acquire backend spinlock.
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/OK3568_Linux_fs/u-boot/common/
H A DKconfig6 Enable recording of boot time while booting. To use it, insert
25 Enable recording of boot time in SPL. To make this visible to U-Boot
26 proper, enable BOOTSTAGE_STASH as well. This will stash the timing
27 information when SPL finishes and load it when U-Boot proper starts
34 Enable output of a boot time report just before the OS is booted.
35 This shows how long it took U-Boot to go through each stage of the
126 Enabling this will make a U-Boot binary that is capable of being
127 booted via NOR. In this case we will enable certain pinmux early
135 Enabling this will make a U-Boot binary that is capable of being
143 Enabling this will make a U-Boot binary that is capable of being
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/OK3568_Linux_fs/kernel/drivers/pci/
H A Dvc.c1 // SPDX-License-Identifier: GPL-2.0
19 * pci_vc_save_restore_dwords - Save or restore a series of dwords
22 * @buf: buffer to save to or restore from
40 * pci_vc_load_arb_table - load and wait for VC arbitration table
63 * pci_vc_load_port_arb_table - Load and wait for VC port arbitration table
66 * @res: VC resource number, ie. VCn (0-7)
91 * pci_vc_enable - Enable virtual channel
94 * @res: VC res number, ie. VCn (0-7)
96 * A VC is enabled by setting the enable bit in matching resource control
98 * end of the link. To keep this simple we enable from the downstream device.
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/OK3568_Linux_fs/kernel/drivers/net/wan/
H A Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
24 #define DMER 0x09 /* DMA Master Enable */
32 #define IER0 0x14 /* Interrupt Enable 0 */
33 #define IER1 0x15 /* Interrupt Enable 1 */
34 #define IER2 0x16 /* Interrupt Enable 2 */
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL 0x00 /* TX/RX buffer L */
49 #define TRBH 0x01 /* TX/RX buffer H */
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/
H A Di915_mitigations.c1 // SPDX-License-Identifier: MIT
40 return -ENOMEM; in mitigations_set()
43 bool enable = true; in mitigations_set() local
61 enable = !enable; in mitigations_set()
66 enable = !enable; in mitigations_set()
75 if (enable) in mitigations_set()
85 err = -EINVAL; in mitigations_set()
97 static int mitigations_get(char *buffer, const struct kernel_param *kp) in mitigations_get() argument
101 bool enable; in mitigations_get() local
104 return scnprintf(buffer, PAGE_SIZE, "%s\n", "off"); in mitigations_get()
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/OK3568_Linux_fs/kernel/drivers/media/platform/omap3isp/
H A Dispstat.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Statistics core
15 #include <linux/dma-mapping.h>
22 #define ISP_STAT_USES_DMAENGINE(stat) ((stat)->dma_ch != NULL)
36 * the next buffer to start to be written in the same point where the overflow
38 * go back to a valid state is having a valid buffer processing. Of course it
39 * requires at least a doubled buffer size to avoid an access to invalid memory
43 * configuration was created. It produces the minimum buffer size for each H3A
45 * will be enabled every time a SBL overflow occur. As the output buffer size
56 #define IS_H3A_AF(stat) ((stat) == &(stat)->isp->isp_af)
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
39 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
52 /* Enable Length/Type error checking for incoming frames. When this option is
60 /* Enable the transmitter. Default: enabled (set) */
63 /* Enable the receiver. Default: enabled (set) */
90 #define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */
91 #define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
150 #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dtonga_ih.c38 * Starting with r6xx, interrupts are handled via a ring buffer.
45 * writes vectors to the ring buffer, it increments the
54 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
58 * Enable the interrupt ring buffer (VI).
67 adev->irq.ih.enabled = true; in tonga_ih_enable_interrupts()
71 * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
75 * Disable the interrupt ring buffer (VI).
87 adev->irq.ih.enabled = false; in tonga_ih_disable_interrupts()
88 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
92 * tonga_ih_irq_init - init and enable the interrupt ring
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/OK3568_Linux_fs/kernel/drivers/input/sensors/accel/
H A Ddmard10.c3 * Copyright (C) 2012-2015 ROCKCHIP.
4 * Author: guoyi <gy@rock-chips.com>
32 #include <linux/sensor-dev.h>
35 #define RBUFF_SIZE 12 /* Rx buffer size */
66 #define VALUE_INTC_Interrupt_En 0x20// INTC[6:5]=b'01 (Data ready interrupt enable, active high at…
145 //g-senor layout configuration, choose one of the following configuration
169 #define DMARD10_BOUNDARY (0x1 << (DMARD10_PRECISION - 1))
182 char buffer[7], buffer2[2]; in gsensor_reset() local
184 buffer[0] = REG_STADR; in gsensor_reset()
187 sensor_rx_data(client, buffer, 2); in gsensor_reset()
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb_82598.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
10 #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
15 #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */
18 #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */
20 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet buffers enable */
21 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores (RSS) enable */
33 #define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */
35 #define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */
37 #define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */
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/OK3568_Linux_fs/u-boot/drivers/usb/host/
H A Dr8a66597.h2 * R8A66597 HCD (Host Controller Driver) for u-boot
6 * SPDX-License-Identifier: GPL-2.0
93 #define HSE 0x0080 /* b7: Hi-speed enable */
95 #define DRPD 0x0020 /* b5: D+/- pull down control */
101 #define USBE 0x0001 /* b0: USB module operation enable */
104 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
105 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
107 #define IDMON 0x0004 /* b3: ID-pin monitor */
108 #define LNST 0x0003 /* b1-0: D+, D- line status */
110 #define FS_KSTS 0x0002 /* Full-Speed K State */
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/OK3568_Linux_fs/kernel/sound/soc/intel/skylake/
H A Dskl-sst-cldma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #define SKL_CL_DMA_SD_INT_COMPLETE 0x04 /* Buffer completion interrupt */
60 /* Interrupt On Completion Enable */
66 /* FIFO Error Interrupt Enable */
72 /* Descriptor Error Interrupt Enable */
110 /* Buffer Completion Interrupt Status */
134 /* CL: Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address */
142 /* Buffer Descriptor List Lower Base Address */
148 /* Buffer Descriptor List Upper Base Address */
155 * Code Loader - Software Position Based FIFO
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/OK3568_Linux_fs/kernel/kernel/trace/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 See Documentation/trace/ftrace-design.rst
21 See Documentation/trace/ftrace-design.rst
26 See Documentation/trace/ftrace-design.rst
37 See Documentation/trace/ftrace-design.rst
42 See Documentation/trace/ftrace-design.rst
47 Arch supports the gcc options -pg with -mfentry
52 Arch supports the gcc options -pg with -mrecord-mcount and -nop-mcount
57 Arch supports objtool --mcount
148 Enable the kernel tracing infrastructure.
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/OK3568_Linux_fs/kernel/sound/firewire/dice/
H A Ddice-proc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dice_proc.c - a part of driver for Dice based devices
11 static int dice_proc_read_mem(struct snd_dice *dice, void *buffer, in dice_proc_read_mem() argument
17 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST, in dice_proc_read_mem()
19 buffer, 4 * quadlets, 0); in dice_proc_read_mem()
24 be32_to_cpus(&((u32 *)buffer)[i]); in dice_proc_read_mem()
45 for (i = 0; i < size - 2; ++i) { in dice_proc_fixup_string()
53 s[size - 1] = '\0'; in dice_proc_fixup_string()
57 struct snd_info_buffer *buffer) in dice_proc_read() argument
70 struct snd_dice *dice = entry->private_data; in dice_proc_read()
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/OK3568_Linux_fs/u-boot/cmd/fastboot/
H A DKconfig10 bool "Enable USB fastboot gadget"
16 bool "Enable fastboot protocol over UDP"
21 bool "Enable FASTBOOT command"
30 See doc/README.android-fastboot for more information.
35 hex "Define FASTBOOT buffer address"
47 The fastboot protocol requires a large memory buffer for
52 hex "Define FASTBOOT buffer size"
58 The fastboot protocol requires a large memory buffer for
59 downloads. This buffer should be as large as possible for a
71 bool "Enable FASTBOOT FLASH command"
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mmhubbub.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
34 mcif_wb20->mcif_wb_regs->reg
37 mcif_wb20->base.ctx
41 mcif_wb20->mcif_wb_shift->field_name, mcif_wb20->mcif_wb_mask->field_name
48 * unsigned long long luma_address[4]; //4 frame buffer
60 …* unsigned int sw_int_en; // Software interrupt enable, frame end and overf…
61 * unsigned int sw_slice_int_en; // slice end interrupt enable
62 * unsigned int sw_overrun_int_en; // overrun error interrupt enable
63 * unsigned int vce_int_en; // VCE interrupt enable, frame end and overflow
64 …* unsigned int vce_slice_int_en; // VCE slice end interrupt enable, frame end and …
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