usb/host/r8a66597.h

2  * R8A66597 HCD (Host Controller Driver) for u-boot
6  * SPDX-License-Identifier:	GPL-2.0
93 #define HSE		0x0080	/* b7: Hi-speed enable */
95 #define DRPD		0x0020	/* b5: D+/- pull down control */
101 #define USBE		0x0001	/* b0: USB module operation enable */
104 #define OVCBIT		0x8000	/* b15-14: Over-current bit */
105 #define OVCMON		0xC000	/* b15-14: Over-current monitor */
107 #define IDMON		0x0004	/* b3: ID-pin monitor */
108 #define LNST		0x0003	/* b1-0: D+, D- line status */
110 #define FS_KSTS		0x0002	/* Full-Speed K State */
111 #define FS_JSTS		0x0001	/* Full-Speed J State */
112 #define LS_JSTS		0x0002	/* Low-Speed J State */
113 #define LS_KSTS		0x0001	/* Low-Speed K State */
121 #define USBRST		0x0040	/* b6: USB reset enable */
122 #define RESUME		0x0020	/* b5: Resume enable */
123 #define UACT		0x0010	/* b4: USB bus enable */
124 #define RHST		0x0007	/* b1-0: Reset handshake status */
126 #define HSMODE		0x0003	/* Hi-Speed mode */
127 #define FSMODE		0x0002	/* Full-Speed mode */
128 #define LSMODE		0x0001	/* Low-Speed mode */
132 #define UTST		0x000F	/* b3-0: Test select */
148 #define INTA		0x0001	/* b1: USB INT-pin active */
154 #define DFORM		0x0380	/* b9-7: DMA mode select */
161 #define DENDE		0x0010	/* b4: Dend enable */
166 #define REW		0x4000	/* b14: Buffer rewind */
167 #define DCLRM		0x2000	/* b13: DMA buffer clear mode */
168 #define DREQE		0x1000	/* b12: DREQ output enable */
177 #define CURPIPE		0x000F	/* b2-0: PIPE select */
180 #define BVAL		0x8000	/* b15: Buffer valid flag */
181 #define BCLR		0x4000	/* b14: Buffer clear */
183 #define DTLN		0x0FFF	/* b11-0: FIFO received data length */
185 /* Interrupt Enable Register 0 */
191 #define BEMPE	0x0400	/* b10: Buffer empty interrupt */
192 #define NRDYE	0x0200	/* b9: Buffer not ready interrupt */
193 #define BRDYE	0x0100	/* b8: Buffer ready interrupt */
195 /* Interrupt Enable Register 1 */
196 #define OVRCRE		0x8000	/* b15: Over-current interrupt */
204 /* BRDY Interrupt Enable/Status Register */
216 /* NRDY Interrupt Enable/Status Register */
228 /* BEMP Interrupt Enable/Status Register */
241 #define TRNENSEL	0x0100	/* b8: Select transaction enable period */
245 #define SOFMODE		0x000C	/* b3-2: SOF pin select */
256 #define BEMP	0x0400	/* b10: Buffer empty interrupt */
257 #define NRDY	0x0200	/* b9: Buffer not ready interrupt */
258 #define BRDY	0x0100	/* b8: Buffer ready interrupt */
260 #define DVSQ	0x0070	/* b6-4: Device state */
270 #define DVSQS		0x0030	/* b5-4: Device state */
272 #define CTSQ		0x0007	/* b2-0: Control transfer stage */
282 #define OVRCR		0x8000	/* b15: Over-current interrupt */
286 #define EOFERR		0x0040	/* b6: EOF-error interrupt */
293 #define FRNM		0x07FF	/* b10-0: Frame number */
296 #define UFRNM		0x0007	/* b2-0: Micro frame number */
300 #define DEVSEL	0xF000	/* b15-14: Device address select */
301 #define MAXP	0x007F	/* b6-0: Maxpacket size of default control pipe */
304 #define BSTS		0x8000	/* b15: Buffer status */
306 #define CSCLR		0x2000	/* b13: complete-split status clear */
307 #define CSSTS		0x1000	/* b12: complete-split status */
313 #define PINGE		0x0010	/* b4: ping enable */
314 #define CCPL		0x0004	/* b2: Enable control transfer complete */
315 #define PID		0x0003	/* b1-0: Response PID */
322 #define PIPENM		0x0007	/* b2-0: Pipe select */
325 #define R8A66597_TYP	0xC000	/* b15-14: Transfer type */
329 #define R8A66597_BFRE	0x0400	/* b10: Buffer ready interrupt mode select */
330 #define R8A66597_DBLB	0x0200	/* b9: Double buffer mode select */
334 #define R8A66597_EPNUM	0x000F	/* b3-0: Eendpoint number select */
336 /* Pipe Buffer Configuration Register */
337 #define BUFSIZE		0x7C00	/* b14-10: Pipe buffer size */
338 #define BUFNMB		0x007F	/* b6-0: Pipe buffer number */
343 #define MXPS	0x07FF	/* b10-0: Maxpacket size */
346 #define IFIS	0x1000	/* b12: Isochronous in-buffer flush mode select */
347 #define IITV	0x0007	/* b2-0: Isochronous interval */
350 #define BSTS	0x8000	/* b15: Buffer status */
351 #define INBUFM	0x4000	/* b14: IN buffer monitor (Only for PIPE1 to 5) */
352 #define CSCLR	0x2000	/* b13: complete-split status clear */
353 #define CSSTS	0x1000	/* b12: complete-split status */
355 #define ACLRM	0x0200	/* b9: Out buffer auto clear mode */
360 #define PID	0x0003	/* b1-0: Response PID */
363 #define TRENB		0x0200	/* b9: Transaction counter enable */
367 #define TRNCNT		0xFFFF	/* b15-0: Transaction counter */
405 	return readw(r8a66597->reg + offset);  in r8a66597_read()
413 	unsigned long fifoaddr = r8a66597->reg + offset;  in r8a66597_read_fifo()
419 		p[i] = readl(r8a66597->reg + offset);  in r8a66597_read_fifo()
431 	writew(val, r8a66597->reg + offset);  in r8a66597_write()
439 	unsigned long fifoaddr = r8a66597->reg + offset;  in r8a66597_write_fifo()
454 				writeb(pb[i], fifoaddr + 3 - i);  in r8a66597_write_fifo()
523 #define get_pipectr_addr(pipenum)	(PIPE1CTR + (pipenum - 1) * 2)
524 #define get_pipetre_addr(pipenum)	(PIPE1TRE + (pipenum - 1) * 4)
525 #define get_pipetrn_addr(pipenum)	(PIPE1TRN + (pipenum - 1) * 4)
528 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */
577 #define RH_REQ_ERR		   -1
584 #define RH_PS_PES	0x00000002	/* port enable status*/
591 #define RH_PS_PESC	0x00020000	/* port enable status change */
599 #define RH_HS_DRWE	0x00008000	/* device remote wakeup enable */
602 #define RH_HS_CRWE	0x80000000	/* clear remote wakeup enable */