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/OK3568_Linux_fs/kernel/drivers/clk/bcm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
61 Enable common clock framework support for the Broadcom Cygnus SoC
70 SoC
87 Enable common clock framework support for the Broadcom Northstar 2 SoC
95 Enable common clock framework support for the Broadcom Stingray SoC
102 dependent clocks
/OK3568_Linux_fs/kernel/drivers/pinctrl/intel/
H A Dpinctrl-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
43 * struct intel_function - Description about a function
55 * struct intel_padgroup - Hardware pad group information
74 * enum - Special treatment for GPIO base in pad group
81 INTEL_GPIO_BASE_ZERO = -2,
82 INTEL_GPIO_BASE_NOMAP = -1,
87 * struct intel_community - Intel pin community description
108 * @pad_map: Optional non-linear mapping of the pads
148 * PIN_GROUP - Declare a pin group
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/OK3568_Linux_fs/kernel/Documentation/sound/kernel-api/
H A Dalsa-driver-api.rst9 ---------------
10 .. kernel-doc:: sound/core/init.c
13 -----------------
14 .. kernel-doc:: sound/core/device.c
17 ---------------------------------------
18 .. kernel-doc:: sound/core/sound.c
21 -------------------------
22 .. kernel-doc:: sound/core/memory.c
23 .. kernel-doc:: sound/core/memalloc.c
30 --------
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/OK3568_Linux_fs/kernel/Documentation/driver-api/memory-devices/
H A Dti-emif.rst1 .. SPDX-License-Identifier: GPL-2.0
32 functions of the driver includes re-configuring AC timing
38 DDR device details and other board dependent and SoC dependent
41 - DDR device details: 'struct ddr_device_info'
42 - Device AC timings: 'struct lpddr2_timings' and 'struct lpddr2_min_tck'
43 - Custom configurations: customizable policy options through
45 - IP revision
46 - PHY type
53 - freq_pre_notify_handling()
54 - freq_post_notify_handling()
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H A Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
14 * Pseudo-SRAM devices
16 GPMC is found on Texas Instruments SoC's (OMAP based)
85 4. read async non-muxed
107 6. read sync non-muxed
131 8. write async non-muxed
157 10. write sync non-muxed
172 Many of gpmc timings are dependent on other gpmc timings (a few
173 gpmc timings purely dependent on other gpmc timings, a reason that
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/reset/
H A Dimg,pistachio-reset.txt5 disable individual IP blocks within the Pistachio SoC using "soft reset"
6 control bits found in the Pistachio SoC top level registers.
8 The actual action taken when soft reset is asserted is hardware dependent.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
25 compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
28 clock-names = "sys";
29 #clock-cells = <1>;
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
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H A Dst,sti-picophyreset.txt5 disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
6 the STi family SoC system configuration registers.
8 The actual action taken when softreset is asserted is hardware dependent.
17 - compatible: Should be "st,stih407-picophyreset"
18 - #reset-cells: 1, see below
22 picophyreset: picophyreset-controller {
23 compatible = "st,stih407-picophyreset";
24 #reset-cells = <1>;
42 include/dt-bindings/reset/stih407-resets.h
H A Dst,sti-softreset.txt5 disable on-chip peripheral controllers such as USB and SATA, using
6 "softreset" control bits found in the STi family SoC system configuration
9 The actual action taken when softreset is asserted is hardware dependent.
18 - compatible: Should be "st,stih407-softreset";
19 - #reset-cells: 1, see below
23 softreset: softreset-controller {
24 #reset-cells = <1>;
25 compatible = "st,stih407-softreset";
44 include/dt-bindings/reset/stih407-resets.h
H A Dst,sti-powerdown.txt5 disable on-chip peripheral controllers such as USB and SATA, using
6 "powerdown" control bits found in the STi family SoC system configuration
10 The actual action taken when powerdown is asserted is hardware dependent.
19 - compatible: Should be "st,stih407-powerdown"
20 - #reset-cells: 1, see below
24 powerdown: powerdown-controller {
25 compatible = "st,stih407-powerdown";
26 #reset-cells = <1>;
45 include/dt-bindings/reset/stih407-resets.h
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dsti-dwmac.txt1 STMicroelectronics SoC DWMAC glue layer controller
10 - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
11 "st,stih407-dwmac", "st,stid127-dwmac".
12 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
14 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 register available on STiH407 SoC.
16 - pinctrl-0: pin-control for all the MII mode supported.
19 - resets : phandle pointing to the system reset controller with correct
21 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
23 - st,tx-retime-src: This specifies which clk is wired up to the mac for
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/OK3568_Linux_fs/kernel/drivers/thermal/st/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
26 functionalities and to access to SoC sensor functionalities. This
27 configuration is fully dependent of MACH_STM32MP157.
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dclockdomain.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2008-2011 Texas Instruments, Inc.
6 * Copyright (C) 2008-2011 Nokia Corporation
22 #include <linux/clk-provider.h>
29 #include "soc.h"
56 if (!strcmp(name, temp_clkdm->name)) { in _clkdm_lookup()
66 * _clkdm_register - register a clockdomain
70 * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
77 if (!clkdm || !clkdm->name) in _clkdm_register()
78 return -EINVAL; in _clkdm_register()
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H A Dprm_common.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Tero Kristo <t-kristo@ti.com>
24 #include <linux/clk-provider.h>
27 #include "soc.h"
45 * actual amount of memory needed for the SoC
70 * prm_ll_data: function pointers to SoC-specific implementations of
86 for (i = 0; i < prcm_irq_setup->nr_regs; i++) { in omap_prcm_events_filter_priority()
88 events[i] & prcm_irq_setup->priority_mask[i]; in omap_prcm_events_filter_priority()
99 * done by the SoC specific individual handlers.
107 int nr_irq = prcm_irq_setup->nr_regs * 32; in omap_prcm_irq_handler()
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/OK3568_Linux_fs/kernel/Documentation/power/powercap/
H A Ddtpm.rst1 .. SPDX-License-Identifier: GPL-2.0
7 On the embedded world, the complexity of the SoC leads to an
46 SoC
48 `-- pkg
50 |-- pd0 (cpu0-3)
52 `-- pd1 (cpu4-5)
56 SoC (400mW - 3100mW)
58 `-- pkg (400mW - 3100mW)
60 |-- pd0 (100mW - 700mW)
62 `-- pd1 (300mW - 2400mW)
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dgpmc-nand.txt7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
23 - nand-bus-width: Set this numeric value to 16 if the hardware
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
30 "hw-romcode" <deprecated> use "ham1" instead
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H A Dorion-nand.txt1 NAND support for Marvell Orion SoC platforms
4 - compatible : "marvell,orion-nand".
5 - reg : Base physical address of the NAND and length of memory mapped
9 - cle : Address line number connected to CLE. Default is 0
10 - ale : Address line number connected to ALE. Default is 1
11 - bank-width : Width in bytes of the device. Default is 1
12 - chip-delay : Chip dependent delay for transferring data from array to read
15 The device tree may optionally contain sub-nodes describing partitions of the
21 #address-cells = <1>;
22 #size-cells = <1>;
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dsamsung-phy.txt1 Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/can/
H A Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - enum:
20 - fsl,imx8qm-flexcan
21 - fsl,imx8mp-flexcan
22 - fsl,imx6q-flexcan
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/
H A Dsocionext,uniphier-mio-dmac.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Masahiro Yamada <yamada.masahiro@socionext.com>
17 - $ref: "dma-controller.yaml#"
21 const: socionext,uniphier-mio-dmac
29 The number of interrupt lines is SoC-dependent.
37 '#dma-cells':
42 - compatible
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/OK3568_Linux_fs/kernel/Documentation/driver-api/thermal/
H A Dcpu-idle-cooling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
10 Under certain circumstances a SoC can reach a critical temperature
12 control. When the SoC has to stabilize the temperature, the kernel can
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
36 duration in a controlled period, the SoC temperature will
58 ---------------
78 |------- -------
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mailbox/
H A Domap-mailbox.txt14 fixed for an instance and are dictated by the IP integration into the SoC
22 All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
25 routed to different processor sub-systems on DRA7xx as they are routed through
35 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
38 --------------------
39 - compatible: Should be one of the following,
40 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
41 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
42 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
44 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
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/OK3568_Linux_fs/kernel/drivers/gpu/arm/midgard/platform/rk/
H A Dmali_kbase_rk.h2 * Rockchip SoC Mali-Midgard platform-dependent codes
20 /*---------------------------------------------------------------------------*/
24 /*---------------------------------------------------------------------------*/
27 * struct rk_context - work_context of platform_dependent_part_of_rk.
53 /*---------------------------------------------------------------------------*/
58 return (struct rk_context *)(kbdev->platform_context); in get_rk_context()
/OK3568_Linux_fs/kernel/Documentation/power/
H A Dopp.rst5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
23 In an operational system executing varied use cases, not all modules in the SoC
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
41 - {300000000, 1000000}
42 - {800000000, 1200000}
43 - {1000000000, 1300000}
46 ----------------------------------------
57 (users) -> registers a set of default OPPs -> (library)
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/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/platform/rk/
H A Dmali_kbase_rk.h2 * Rockchip SoC Mali-Midgard platform-dependent codes
20 /*---------------------------------------------------------------------------*/
24 /*---------------------------------------------------------------------------*/
27 * struct rk_context - work_context of platform_dependent_part_of_rk.
58 /*---------------------------------------------------------------------------*/
63 return (struct rk_context *)(kbdev->platform_context); in get_rk_context()
/OK3568_Linux_fs/u-boot/arch/x86/include/asm/arch-quark/
H A Dquark.h4 * SPDX-License-Identifier: GPL-2.0+
118 /* Port 0x31: SoC Unit Port Registers */
176 /* USB EHCI memory-mapped registers */
179 /* USB device memory-mapped registers */
201 * qrk_pci_read_config_dword() - Read a configuration value
217 * qrk_pci_write_config_dword() - Write a PCI configuration value
233 * board_assert_perst() - Assert the PERST# pin
235 * The CPU interface to the PERST# signal on Quark is platform dependent.
236 * Board-specific codes need supply this routine to assert PCIe slot reset.
246 * board_deassert_perst() - De-assert the PERST# pin
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