Searched full:dpdma (Results 1 – 9 of 9) sorted by relevance
3 * Xilinx ZynqMP DPDMA Engine driver27 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>32 /* DPDMA registers */118 /* DPDMA descriptor fields */141 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor179 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor180 * @hw: DPDMA hardware descriptor191 * struct xilinx_dpdma_tx_desc - DPDMA transaction descriptor208 * struct xilinx_dpdma_chan - DPDMA channel222 * @xdev: DPDMA device[all …]
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#25 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h29 const: xlnx,zynqmp-dpdma59 compatible = "xlnx,zynqmp-dpdma";
24 /* The DPDMA is limited to 44 bit addressing. */
50 * | DPDMA | --->| | --> | Video | Video +-------------+ |64 * Only non-live input from the DPDMA and output to the DisplayPort Source68 * The display controller code creates planes for the DPDMA video and graphics
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
695 tristate "Xilinx DPDMA Engine"
1048 compatible = "xlnx,dpdma";
19343 XILINX ZYNQMP DPDMA DRIVER19348 F: Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml19350 F: include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
pax_global_header u-boot-2021.07/ u-boot-2021.07/.azure-pipelines.yml ...