1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ZynqMP Display Driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017 - 2020 Xilinx, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Authors: 8*4882a593Smuzhiyun * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9*4882a593Smuzhiyun * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _ZYNQMP_DISP_H_ 13*4882a593Smuzhiyun #define _ZYNQMP_DISP_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <linux/types.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * 3840x2160 is advertised as the maximum resolution, but almost any 19*4882a593Smuzhiyun * resolutions under a 300Mhz pixel rate would work. Pick 4096x4096. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #define ZYNQMP_DISP_MAX_WIDTH 4096 22*4882a593Smuzhiyun #define ZYNQMP_DISP_MAX_HEIGHT 4096 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* The DPDMA is limited to 44 bit addressing. */ 25*4882a593Smuzhiyun #define ZYNQMP_DISP_MAX_DMA_BIT 44 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct device; 28*4882a593Smuzhiyun struct drm_device; 29*4882a593Smuzhiyun struct platform_device; 30*4882a593Smuzhiyun struct zynqmp_disp; 31*4882a593Smuzhiyun struct zynqmp_dpsub; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun void zynqmp_disp_handle_vblank(struct zynqmp_disp *disp); 34*4882a593Smuzhiyun bool zynqmp_disp_audio_enabled(struct zynqmp_disp *disp); 35*4882a593Smuzhiyun unsigned int zynqmp_disp_get_audio_clk_rate(struct zynqmp_disp *disp); 36*4882a593Smuzhiyun uint32_t zynqmp_disp_get_crtc_mask(struct zynqmp_disp *disp); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun int zynqmp_disp_drm_init(struct zynqmp_dpsub *dpsub); 39*4882a593Smuzhiyun int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub, struct drm_device *drm); 40*4882a593Smuzhiyun void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #endif /* _ZYNQMP_DISP_H_ */ 43