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/rk3399_rockchip-uboot/tools/patman/test/
H A Dtest01.txt3 Date: Sat Apr 15 15:39:08 2017 -0600
10 ‘long long unsigned int’, but argument 3 has type
11 ‘u64 {aka long unsigned int}’ [-Wformat=]
15 Signed-off-by: Simon Glass <sjg@chromium.org>
16 Series-notes:
22 Commit-notes:
29 Date: Sat Apr 15 15:39:08 2017 -0600
36 ‘long long unsigned int’, but argument 3 has type
37 ‘long unsigned int’ [-Wformat=]
41 Signed-off-by: Simon Glass <sjg@chromium.org>
[all …]
H A D0000-cover-letter.patch3 Date: Sat, 27 May 2017 20:52:11 -0600
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
15 cmd/pci.c | 3 ++-
18 lib/fdtdec.c | 3 ++-
19 4 files changed, 6 insertions(+), 2 deletions(-)
21 --
/rk3399_rockchip-uboot/board/hisilicon/poplar/
H A DREADME6 integrated quad-core 64-bit ARM Cortex A53 processor and high
8 set-top solution based on Linux or Android. Its high performance
13 CPU Quad-core ARM Cortex-A53 64 bit
14 DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
16 CONSOLE USB-micro port for console support
19 JTAG 8-Pin JTAG
33 U-boot has a *strong* dependency with the l-loader and the arm trusted firmware
37 l-loader --> arm_trusted_firmware --> u-boot
39 U-Boot needs to be aware of the BL31 runtime location and size to avoid writing
43 The current version of u-boot has been tested with:
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dbootrom.h2 * (C) Copyright 2017 Heiko Stuebner <heiko@sntech.de>
3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
5 * SPDX-License-Identifier: GPL-2.0
18 * back_to_bootrom() - return to bootrom (for TPL/SPL), passing a
37 BROM_BOOT_NEXTSTAGE = 1, /* continue boot-sequence */
38 BROM_BOOT_ENTER_DNL, /* have BROM enter download-mode */
44 * Boot-device identifiers as used by the BROM
50 BROM_BOOTSOURCE_SPINOR = 3,
63 * Locations of the boot-device identifier in SRAM
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-bcmcygnus/
H A Dconfigs.h2 * Copyright 2014-2017 Broadcom.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/iproc-common/configs.h>
15 /* Post pad 3 bytes after each reg addr */
16 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
22 #define CONFIG_CONS_INDEX 3
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3368/
H A Dsyscon_rk3368.c2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
6 * SPDX-License-Identifier: GPL-2.0+
15 { .compatible = "rockchip,rk3368-grf",
17 { .compatible = "rockchip,rk3368-pmugrf",
19 { .compatible = "rockchip,rk3368-msch",
21 { .compatible = "rockchip,rk3368-sgrf",
38 dev->driver_data = dev->driver->of_match->data; in rk3368_syscon_bind_of_platdata()
39 debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); in rk3368_syscon_bind_of_platdata()
[all …]
/rk3399_rockchip-uboot/drivers/rknand/
H A DKconfig2 # Copyright (C) (C) Copyright 2016-2017 Rockchip Electronics Co., Ltd
4 # SPDX-License-Identifier: GPL-2.0+
16 bool "Rockchip ZFTL for rkpx30/rk3326 to support 3D/2D TLC/MLC"
21 It supports block interface(with zftl) to read and write 3D/2D TLC/MLC
/rk3399_rockchip-uboot/board/renesas/ulcb/
H A Dcpld.c4 * Copyright (C) 2017 Renesas Electronics Corporation
5 * Copyright (C) 2017 Cogent Embedded, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
97 /* PULL-UP on MISO line */ in cpld_init()
134 if (argc < 3) in do_cpld()
145 if (argc == 3 && strcmp(argv[1], "read") == 0) { in do_cpld()
148 val = simple_strtoul(argv[3], NULL, 16); in do_cpld()
/rk3399_rockchip-uboot/include/dt-bindings/power-domain/
H A Dbcm6328-power-domain.h2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
13 #define BCM6328_PWR_SAR 3
H A Dbcm63268-power-domain.h2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
13 #define BCM63268_PWR_DECT 3
/rk3399_rockchip-uboot/include/configs/
H A Dedison.h2 * Copyright (c) 2017 Intel Corp.
4 * SPDX-License-Identifier: GPL-2.0+
30 #define CONFIG_NR_DRAM_BANKS 3
46 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
/rk3399_rockchip-uboot/include/dt-bindings/reset/
H A Dbcm6338-reset.h2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
6 * SPDX-License-Identifier: GPL-2.0+
14 #define BCM6338_RST_USBH 3
H A Dbcm6348-reset.h2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
6 * SPDX-License-Identifier: GPL-2.0+
14 #define BCM6348_RST_USBH 3
H A Dbcm6358-reset.h2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
6 * SPDX-License-Identifier: GPL-2.0+
14 #define BCM6358_RST_MPI 3
H A Dbcm6328-reset.h2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
6 * SPDX-License-Identifier: GPL-2.0+
15 #define BCM6328_RST_ENETSW 3
/rk3399_rockchip-uboot/include/dt-bindings/clock/
H A Dbcm6348-clock.h2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
6 * SPDX-License-Identifier: GPL-2.0+
15 #define BCM6348_CLK_M2M 3
H A Dbcm3380-clock.h2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
7 * SPDX-License-Identifier: GPL-2.0+
16 #define BCM3380_CLK0_EPHY 3
H A Dbcm63268-clock.h2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
6 * SPDX-License-Identifier: GPL-2.0+
15 #define BCM63268_CLK_VDSL 3
39 #define BCM63268_TCLK_GPHY 3
H A Dbcm6328-clock.h2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
6 * SPDX-License-Identifier: GPL-2.0+
15 #define BCM6328_CLK_ADSL 3
/rk3399_rockchip-uboot/arch/arm/mach-socfpga/include/mach/
H A Dfpga_manager_gen5.h2 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
5 * SPDX-License-Identifier: BSD-3-Clause
13 #define FPGAMGRREGS_STAT_MSEL_LSB 3
22 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
58 u32 _pad_0x854_0x85c[3];
H A Dsystem_manager_arria10.h2 * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
4 * SPDX-License-Identifier: GPL-2.0
16 u32 _pad_0x14_0x1f[3];
26 u32 emac[3];
33 u32 _pad_0x74_0x7f[3];
/rk3399_rockchip-uboot/tools/dtoc/
H A Ddtoc_test_addr32.dts4 * Copyright 2017 Google, Inc
6 * SPDX-License-Identifier: GPL-2.0+
9 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
16 u-boot,dm-pre-reloc;
22 u-boot,dm-pre-reloc;
24 reg = <0x12345678 0x98765432 2 3>;
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3128/
H A Drk3128.c2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
17 ((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
28 writel(CPU_AXI_QOS_PRIORITY_LEVEL(3, 3), CPU_AXI_QOS_PRIORITY_BASE); in arch_cpu_init()
41 writel(CPU_AXI_QOS_PRIORITY_LEVEL(3, 3), CPU_AXI_CIF_QOS_PRIORITY_BASE); in arch_cpu_init()
67 rk_clrsetreg(&grf->gpio1c_iomux, in board_debug_uart_init()
69 rk_clrsetreg(&grf->gpio1c_iomux, in board_debug_uart_init()
/rk3399_rockchip-uboot/board/intel/edison/
H A Dconfig.mk3 # Copyright (c) 2017 Intel Corporation
5 # SPDX-License-Identifier: GPL-2.0 BSD-3-Clause
8 # Add 4096 bytes of zeroes to u-boot.bin
14 ALL-y += u-boot-align.bin
15 u-boot-align.bin: u-boot.bin
18 HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
/rk3399_rockchip-uboot/include/dt-bindings/power/
H A Dpx30-power.h2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 #define PX30_PD_A35_3 3

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