1*6867e19aSTien Fong Chee /* 2*6867e19aSTien Fong Chee * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 3*6867e19aSTien Fong Chee * All rights reserved. 4*6867e19aSTien Fong Chee * 5*6867e19aSTien Fong Chee * SPDX-License-Identifier: BSD-3-Clause 6*6867e19aSTien Fong Chee */ 7*6867e19aSTien Fong Chee 8*6867e19aSTien Fong Chee #ifndef _FPGA_MANAGER_GEN5_H_ 9*6867e19aSTien Fong Chee #define _FPGA_MANAGER_GEN5_H_ 10*6867e19aSTien Fong Chee 11*6867e19aSTien Fong Chee #define FPGAMGRREGS_STAT_MODE_MASK 0x7 12*6867e19aSTien Fong Chee #define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 13*6867e19aSTien Fong Chee #define FPGAMGRREGS_STAT_MSEL_LSB 3 14*6867e19aSTien Fong Chee 15*6867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9) 16*6867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8) 17*6867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2) 18*6867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_NCE_MASK BIT(1) 19*6867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_EN_MASK BIT(0) 20*6867e19aSTien Fong Chee #define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 21*6867e19aSTien Fong Chee 22*6867e19aSTien Fong Chee #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3) 23*6867e19aSTien Fong Chee #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2) 24*6867e19aSTien Fong Chee #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1) 25*6867e19aSTien Fong Chee #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0) 26*6867e19aSTien Fong Chee 27*6867e19aSTien Fong Chee /* FPGA Mode */ 28*6867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_FPGAOFF 0x0 29*6867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_RESETPHASE 0x1 30*6867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_CFGPHASE 0x2 31*6867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_INITPHASE 0x3 32*6867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_USERMODE 0x4 33*6867e19aSTien Fong Chee #define FPGAMGRREGS_MODE_UNKNOWN 0x5 34*6867e19aSTien Fong Chee 35*6867e19aSTien Fong Chee #ifndef __ASSEMBLY__ 36*6867e19aSTien Fong Chee 37*6867e19aSTien Fong Chee struct socfpga_fpga_manager { 38*6867e19aSTien Fong Chee /* FPGA Manager Module */ 39*6867e19aSTien Fong Chee u32 stat; /* 0x00 */ 40*6867e19aSTien Fong Chee u32 ctrl; 41*6867e19aSTien Fong Chee u32 dclkcnt; 42*6867e19aSTien Fong Chee u32 dclkstat; 43*6867e19aSTien Fong Chee u32 gpo; /* 0x10 */ 44*6867e19aSTien Fong Chee u32 gpi; 45*6867e19aSTien Fong Chee u32 misci; /* 0x18 */ 46*6867e19aSTien Fong Chee u32 _pad_0x1c_0x82c[517]; 47*6867e19aSTien Fong Chee 48*6867e19aSTien Fong Chee /* Configuration Monitor (MON) Registers */ 49*6867e19aSTien Fong Chee u32 gpio_inten; /* 0x830 */ 50*6867e19aSTien Fong Chee u32 gpio_intmask; 51*6867e19aSTien Fong Chee u32 gpio_inttype_level; 52*6867e19aSTien Fong Chee u32 gpio_int_polarity; 53*6867e19aSTien Fong Chee u32 gpio_intstatus; /* 0x840 */ 54*6867e19aSTien Fong Chee u32 gpio_raw_intstatus; 55*6867e19aSTien Fong Chee u32 _pad_0x848; 56*6867e19aSTien Fong Chee u32 gpio_porta_eoi; 57*6867e19aSTien Fong Chee u32 gpio_ext_porta; /* 0x850 */ 58*6867e19aSTien Fong Chee u32 _pad_0x854_0x85c[3]; 59*6867e19aSTien Fong Chee u32 gpio_1s_sync; /* 0x860 */ 60*6867e19aSTien Fong Chee u32 _pad_0x864_0x868[2]; 61*6867e19aSTien Fong Chee u32 gpio_ver_id_code; 62*6867e19aSTien Fong Chee u32 gpio_config_reg2; /* 0x870 */ 63*6867e19aSTien Fong Chee u32 gpio_config_reg1; 64*6867e19aSTien Fong Chee }; 65*6867e19aSTien Fong Chee 66*6867e19aSTien Fong Chee #endif /* __ASSEMBLY__ */ 67*6867e19aSTien Fong Chee 68*6867e19aSTien Fong Chee #endif /* _FPGA_MANAGER_GEN5_H_ */ 69