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/optee_os/lib/libmbedtls/mbedtls/include/mbedtls/
H A Dconfig_adjust_psa_from_legacy.h37 #define MBEDTLS_PSA_BUILTIN_ALG_CCM 1
38 #define PSA_WANT_ALG_CCM 1
40 #define MBEDTLS_PSA_BUILTIN_ALG_CCM_STAR_NO_TAG 1
41 #define PSA_WANT_ALG_CCM_STAR_NO_TAG 1
46 #define MBEDTLS_PSA_BUILTIN_ALG_CMAC 1
47 #define PSA_WANT_ALG_CMAC 1
51 #define MBEDTLS_PSA_BUILTIN_ALG_ECDH 1
52 #define PSA_WANT_ALG_ECDH 1
56 #define MBEDTLS_PSA_BUILTIN_ALG_ECDSA 1
57 #define PSA_WANT_ALG_ECDSA 1
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H A Dsha1.h4 * \brief This file contains SHA-1 definitions and functions.
6 * The Secure Hash Algorithm 1 (SHA-1) cryptographic hash function is defined in
9 * \warning SHA-1 is considered a weak message digest and its use constitutes
26 /** SHA-1 input data was malformed. */
38 * \brief The SHA-1 context structure.
40 * \warning SHA-1 is considered a weak message digest and its use
57 * \brief This function initializes a SHA-1 context.
59 * \warning SHA-1 is considered a weak message digest and its use
63 * \param ctx The SHA-1 context to initialize.
70 * \brief This function clears a SHA-1 context.
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H A Dconfig_adjust_legacy_from_psa.h51 * 1. Check if acceleration is complete for curves, key types, algs.
132 #define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_256 1
141 #define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_384 1
150 #define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_512 1
159 #define MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_255 1
168 #define MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_448 1
177 #define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_192 1
186 #define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_224 1
195 #define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_256 1
204 #define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_384 1
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H A Doid.h37 #define MBEDTLS_OID_X509_EXT_AUTHORITY_KEY_IDENTIFIER (1 << 0)
38 #define MBEDTLS_OID_X509_EXT_SUBJECT_KEY_IDENTIFIER (1 << 1)
39 #define MBEDTLS_OID_X509_EXT_KEY_USAGE (1 << 2)
40 #define MBEDTLS_OID_X509_EXT_CERTIFICATE_POLICIES (1 << 3)
41 #define MBEDTLS_OID_X509_EXT_POLICY_MAPPINGS (1 << 4)
42 #define MBEDTLS_OID_X509_EXT_SUBJECT_ALT_NAME (1 << 5)
43 #define MBEDTLS_OID_X509_EXT_ISSUER_ALT_NAME (1 << 6)
44 #define MBEDTLS_OID_X509_EXT_SUBJECT_DIRECTORY_ATTRS (1 << 7)
45 #define MBEDTLS_OID_X509_EXT_BASIC_CONSTRAINTS (1 << 8)
46 #define MBEDTLS_OID_X509_EXT_NAME_CONSTRAINTS (1 << 9)
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/optee_os/lib/libmbedtls/mbedtls/include/psa/
H A Dcrypto_config.h41 #define PSA_WANT_ALG_CBC_NO_PADDING 1
42 #define PSA_WANT_ALG_CBC_PKCS7 1
43 #define PSA_WANT_ALG_CCM 1
44 #define PSA_WANT_ALG_CCM_STAR_NO_TAG 1
45 #define PSA_WANT_ALG_CMAC 1
46 #define PSA_WANT_ALG_CFB 1
47 #define PSA_WANT_ALG_CHACHA20_POLY1305 1
48 #define PSA_WANT_ALG_CTR 1
49 #define PSA_WANT_ALG_DETERMINISTIC_ECDSA 1
50 #define PSA_WANT_ALG_ECB_NO_PADDING 1
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/optee_os/core/arch/arm/dts/
H A Dsama7g5-pinfunc.h11 #define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1)
12 #define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1)
13 #define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1)
15 #define PIN_PA1 1
17 #define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1)
18 #define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1)
19 #define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1)
20 #define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1)
24 #define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1)
25 #define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1)
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H A Dsama5d2-pinfunc.h11 #define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1)
12 #define PIN_PA0__QSPI0_SCK PINMUX_PIN(PIN_PA0, 2, 1)
14 #define PIN_PA1 1
16 #define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1)
17 #define PIN_PA1__QSPI0_CS PINMUX_PIN(PIN_PA1, 2, 1)
21 #define PIN_PA2__SDMMC0_DAT0 PINMUX_PIN(PIN_PA2, 1, 1)
22 #define PIN_PA2__QSPI0_IO0 PINMUX_PIN(PIN_PA2, 2, 1)
26 #define PIN_PA3__SDMMC0_DAT1 PINMUX_PIN(PIN_PA3, 1, 1)
27 #define PIN_PA3__QSPI0_IO1 PINMUX_PIN(PIN_PA3, 2, 1)
31 #define PIN_PA4__SDMMC0_DAT2 PINMUX_PIN(PIN_PA4, 1, 1)
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H A Dfsl-lx2160a-qds.dts33 mdio-mux-1 {
37 #address-cells=<1>;
40 mdio@0 { /* On-board PHY #1 RGMI1*/
42 #address-cells = <1>;
48 #address-cells = <1>;
52 mdio@18 { /* Slot #1 */
54 #address-cells = <1>;
60 #address-cells = <1>;
64 mdio@1a { /* Slot #3 */
66 #address-cells = <1>;
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H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi28 DIV_CFG(DIV_LSMCU, 1)
38 FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
39 FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
43 FLEXGEN_CFG(6, XBAR_SRC_PLL4, 0, 1)
66 FLEXGEN_CFG(29, XBAR_SRC_PLL5, 0, 1)
67 FLEXGEN_CFG(30, XBAR_SRC_HSE_KER, 0, 1)
93 FLEXGEN_CFG(57, XBAR_SRC_HSE_KER, 0, 1)
94 FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1)
95 FLEXGEN_CFG(59, XBAR_SRC_PLL4, 0, 1)
117 pll1: st,pll-1 {
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/optee_os/lib/libmbedtls/mbedtls/library/
H A Dpkwrite.h29 * SubjectPublicKeyInfo ::= SEQUENCE { 1 + 3
30 * algorithm AlgorithmIdentifier, 1 + 1 (sequence)
31 * + 1 + 1 + 9 (rsa oid)
32 * + 1 + 1 (params null)
33 * subjectPublicKey BIT STRING } 1 + 3 + (1 + below)
34 * RSAPublicKey ::= SEQUENCE { 1 + 3
35 * modulus INTEGER, -- n 1 + 3 + MPI_MAX + 1
36 * publicExponent INTEGER -- e 1 + 3 + MPI_MAX + 1
43 * RSAPrivateKey ::= SEQUENCE { 1 + 3
44 * version Version, 1 + 1 + 1
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H A Drsa_alt_helpers.c21 * Setting F := lcm(P-1,Q-1), the idea is as follows:
23 * (a) For any 1 <= X < N with gcd(X,N)=1, we have X^F = 1 modulo N, so X^(F/2)
24 * is a square root of 1 in Z/NZ. Since Z/NZ ~= Z/PZ x Z/QZ by CRT and the
25 * square roots of 1 in Z/PZ and Z/QZ are +1 and -1, this leaves the four
26 * possibilities X^(F/2) = (+-1, +-1). If it happens that X^(F/2) = (-1,+1)
27 * or (+1,-1), then gcd(X^(F/2) + 1, N) will be equal to one of the prime
32 * roots of 1 in Z/NZ.
36 * if and only if DE - 1 is a multiple of F, say DE - 1 = F * L.
39 * DE - 1 = FL = (F/2) * (2^(t+1)) * K,
43 * (DE - 1) >> 1, (DE - 1) >> 2, ..., (DE - 1) >> ord
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/optee_os/lib/libutils/isoc/arch/arm/softfloat/source/
H A Ds_countLeadingZeros8.c14 1. Redistributions of source code must retain the above copyright notice,
47 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
48 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
49 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
50 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
/optee_os/core/arch/arm/kernel/
H A Darm32_sysreg.txt12 AIDR c0 1 c0 7 RO IMPLEMENTATION DEFINED Auxiliary ID Register
13 CCSIDR c0 1 c0 0 RO Cache Size ID Registers
14 CLIDR c0 1 c0 1 RO Cache Level ID Register
16 CTR c0 0 c0 1 RO Cache Type Register
20 ID_ISAR1 c0 0 c2 1 RO Instruction Set Attribute Register 1
26 ID_MMFR1 c0 0 c1 5 RO Memory Model Feature Register 1
30 ID_PFR1 c0 0 c1 1 RO Processor Feature Register 1
39 AMAIR1 c10 0 c3 1 RW Auxiliary Memory Attribute Indirection Register 1
40 CONTEXTIDR c13 0 c0 1 RW Context ID Register
43 MAIR1 c10 0 c2 1 RW Memory Attribute Indirection Register 1
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/optee_os/mk/
H A Dsubdir.mk24 uniq = $(if $1,$(firstword $1) $(call uniq,$(filter-out $(firstword $1),$1)))
27 # $1 is local source file name
29 cflags-$(2) := $$(cflags-y) $$(cflags-$(1)-y)
30 cflags-remove-$(2) := $$(cflags-remove-y) $$(cflags-remove-$(1)-y)
31 cxxflags-$(2) := $$(cxxflags-y) $$(cxxflags-$(1)-y)
32 cxxflags-remove-$(2) := $$(cxxflags-remove-y) $$(cxxflags-remove-$(1)-y)
33 cppflags-$(2) := $$(cppflags-y) $$(cppflags-$(1)-y)
34 cppflags-remove-$(2) := $$(cppflags-remove-y) $$(cppflags-remove-$(1)-y)
35 aflags-$(2) := $$(aflags-y) $$(aflags-$(1)-y)
36 aflags-remove-$(2) := $$(aflags-remove-y) $$(aflags-remove-$(1)-y)
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H A Dcheckconf.mk18 $(call cfg-vars-by-prefix,$1), \
34 $(call cfg-vars-by-prefix,$1), \
60 $(strip $(if $(1),$(call _cfg-vars-by-prefix,$(1)),
65 $(sort $(foreach prefix,$(1),$(filter $(prefix)%,$(.VARIABLES))))
70 # y => 1
73 $(strip $(if $(filter y,$($1)),
74 #define $1 1_nl_,
75 $(if $(filter xn x,x$($1)),
76 /* $1 is not set */_nl_,
77 #define $1 $($1)_nl_)))
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/optee_os/core/pta/tests/
H A Dmisc.c37 return -1; in self_test_add_overflow()
39 return -1; in self_test_add_overflow()
41 return -1; in self_test_add_overflow()
43 return -1; in self_test_add_overflow()
45 return -1; in self_test_add_overflow()
46 if (!ADD_OVERFLOW(UINT32_MAX / 2 + 1, UINT32_MAX / 2 + 1, &r_u32)) in self_test_add_overflow()
47 return -1; in self_test_add_overflow()
48 if (ADD_OVERFLOW(UINT32_MAX / 2, UINT32_MAX / 2 + 1, &r_u32)) in self_test_add_overflow()
49 return -1; in self_test_add_overflow()
51 return -1; in self_test_add_overflow()
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/optee_os/lib/libutils/compiler-rt/lib/builtins/
H A Dint_div_impl.inc20 // 0 <= sr <= N - 1 or sr is very large.
21 if (sr > N - 1) // n < d
23 if (sr == N - 1) // d == 1
26 // 1 <= sr <= N - 1. Shifts do not trigger UB.
31 r = (r << 1) | (n >> (N - 1));
32 n = (n << 1) | carry;
35 // if (r >= d) r -= d, carry = 1;
36 const fixint_t s = (fixint_t)(d - r - 1) >> (N - 1);
37 carry = s & 1;
40 n = (n << 1) | carry;
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/optee_os/core/lib/libtomcrypt/src/pk/dsa/
H A Ddsa_export.c23 unsigned char flags[1]; in dsa_export()
40 LTC_ASN1_SHORT_INTEGER, 1UL, &zero, in dsa_export()
41 LTC_ASN1_INTEGER, 1UL, key->p, in dsa_export()
42 LTC_ASN1_INTEGER, 1UL, key->q, in dsa_export()
43 LTC_ASN1_INTEGER, 1UL, key->g, in dsa_export()
44 LTC_ASN1_INTEGER, 1UL, key->y, in dsa_export()
45 LTC_ASN1_INTEGER, 1UL, key->x, in dsa_export()
48 flags[0] = 1; in dsa_export()
50 LTC_ASN1_BIT_STRING, 1UL, flags, in dsa_export()
51 LTC_ASN1_INTEGER, 1UL, key->g, in dsa_export()
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H A Ddsa_import.c24 unsigned char flags[1]; in dsa_import()
36 err = der_decode_sequence_multi(in, inlen, LTC_ASN1_BIT_STRING, 1UL, flags, in dsa_import()
41 if (flags[0] == 1) { in dsa_import()
43 LTC_ASN1_BIT_STRING, 1UL, flags, in dsa_import()
44 LTC_ASN1_INTEGER, 1UL, key->g, in dsa_import()
45 LTC_ASN1_INTEGER, 1UL, key->p, in dsa_import()
46 LTC_ASN1_INTEGER, 1UL, key->q, in dsa_import()
47 LTC_ASN1_INTEGER, 1UL, key->y, in dsa_import()
48 LTC_ASN1_INTEGER, 1UL, key->x, in dsa_import()
58 LTC_ASN1_BIT_STRING, 1UL, flags, in dsa_import()
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/optee_os/core/drivers/
H A Dpl011.c37 #define UART_FR_RTXDIS (1 << 13)
38 #define UART_FR_TERI (1 << 12)
39 #define UART_FR_DDCD (1 << 11)
40 #define UART_FR_DDSR (1 << 10)
41 #define UART_FR_DCTS (1 << 9)
42 #define UART_FR_RI (1 << 8)
43 #define UART_FR_TXFE (1 << 7)
44 #define UART_FR_RXFF (1 << 6)
45 #define UART_FR_TXFF (1 << 5)
46 #define UART_FR_RXFE (1 << 4)
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H A Dimx_uart.c10 * 1. Redistributions of source code must retain the above copyright notice,
41 #define UCR1 0x80 /* Control Register 1 */
46 #define USR1 0x94 /* Status Register 1 */
57 #define URXD_CHARRDY (1<<15)
58 #define URXD_ERR (1<<14)
59 #define URXD_OVRRUN (1<<13)
60 #define URXD_FRMERR (1<<12)
61 #define URXD_BRK (1<<11)
62 #define URXD_PRERR (1<<10)
64 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
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/optee_os/core/lib/libtomcrypt/src/ciphers/twofish/
H A Dtwofish.c52 { 1, 1, 0, 0, 1 },
53 { 0, 1, 1, 0, 0 },
54 { 0, 0, 0, 1, 1 },
55 { 1, 0, 1, 1, 0 }
100 /* b1 = a0 ^ ROR(b0, 1) ^ 8a0 */ in s_sbox()
101 b1 = (a0 ^ ((b0<<3)|(b0>>1)) ^ (a0<<3)) & 15; in s_sbox()
105 b2 = qbox[i][1][(int)b1]; in s_sbox()
110 /* b3 = a2 ^ ROR(b2, 1) ^ 8a2 */ in s_sbox()
111 b3 = (a2 ^ ((b2<<3)|(b2>>1)) ^ (a2<<3)) & 15; in s_sbox()
141 P[1] = p; in gf_mult()
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/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp13-clksrc.h11 #define CMD_MUX 1
40 #define DIV_PLL2DIVP 1
84 #define MUX_AXI 1
135 #define CLK_MPU_HSE CLKSRC(MUX_MPU, 1)
140 #define CLK_AXI_HSE CLKSRC(MUX_AXI, 1)
144 #define CLK_MLAHBS_HSE CLKSRC(MUX_MLAHB, 1)
149 #define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1)
152 #define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1)
156 #define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1)
160 #define CLK_RTC_LSE CLKSRC(MUX_RTC, 1)
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/optee_os/core/arch/arm/crypto/
H A Dsha256_armv8a_ce_a32.S57 subs r2, r2, #1
67 add_update 1, 0, 1, 2, 3
68 add_update 0, 1, 2, 3, 0
69 add_update 1, 2, 3, 0, 1
70 add_update 0, 3, 0, 1, 2
71 add_update 1, 0, 1, 2, 3
72 add_update 0, 1, 2, 3, 0
73 add_update 1, 2, 3, 0, 1
74 add_update 0, 3, 0, 1, 2
75 add_update 1, 0, 1, 2, 3
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H A Dsha512_armv8a_ce_a64.S12 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
117 sub w2, w2, #1
141 dround 0, 1, 2, 3, 4, 20, 24, 12, 13, 19, 16, 17
142 dround 3, 0, 4, 2, 1, 21, 25, 13, 14, 12, 17, 18
143 dround 2, 3, 1, 4, 0, 22, 26, 14, 15, 13, 18, 19
144 dround 4, 2, 0, 1, 3, 23, 27, 15, 16, 14, 19, 12
145 dround 1, 4, 3, 0, 2, 24, 28, 16, 17, 15, 12, 13
147 dround 0, 1, 2, 3, 4, 25, 29, 17, 18, 16, 13, 14
148 dround 3, 0, 4, 2, 1, 26, 30, 18, 19, 17, 14, 15
149 dround 2, 3, 1, 4, 0, 27, 31, 19, 12, 18, 15, 16
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