Lines Matching full:1
33 mdio-mux-1 {
37 #address-cells=<1>;
40 mdio@0 { /* On-board PHY #1 RGMI1*/
42 #address-cells = <1>;
48 #address-cells = <1>;
52 mdio@18 { /* Slot #1 */
54 #address-cells = <1>;
60 #address-cells = <1>;
64 mdio@1a { /* Slot #3 */
66 #address-cells = <1>;
70 mdio@1b { /* Slot #4 */
72 #address-cells = <1>;
76 mdio@1c { /* Slot #5 */
78 #address-cells = <1>;
82 mdio@1d { /* Slot #6 */
84 #address-cells = <1>;
88 mdio@1e { /* Slot #7 */
90 #address-cells = <1>;
94 mdio@1f { /* Slot #8 */
96 #address-cells = <1>;
103 mux-controls = <&mux 1>;
105 #address-cells=<1>;
108 mdio@0 { /* Slot #1 (secondary EMI) */
110 #address-cells = <1>;
114 mdio@1 { /* Slot #2 (secondary EMI) */
116 #address-cells = <1>;
122 #address-cells = <1>;
128 #address-cells = <1>;
134 #address-cells = <1>;
140 #address-cells = <1>;
146 #address-cells = <1>;
152 #address-cells = <1>;
174 #address-cells = <1>;
175 #size-cells = <1>;
186 #address-cells = <1>;
187 #size-cells = <1>;
198 #address-cells = <1>;
199 #size-cells = <1>;
232 #mux-control-cells = <1>;
234 <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
241 #address-cells = <1>;
245 #address-cells = <1>;
263 #address-cells = <1>;