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10 * 1. Redistributions of source code must retain the above copyright notice,
41 #define UCR1 0x80 /* Control Register 1 */
46 #define USR1 0x94 /* Status Register 1 */
57 #define URXD_CHARRDY (1<<15)
58 #define URXD_ERR (1<<14)
59 #define URXD_OVRRUN (1<<13)
60 #define URXD_FRMERR (1<<12)
61 #define URXD_BRK (1<<11)
62 #define URXD_PRERR (1<<10)
64 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
65 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
66 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
67 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
68 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
69 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
70 #define UCR1_IREN (1<<7) /* Infrared interface enable */
71 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
72 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
73 #define UCR1_SNDBRK (1<<4) /* Send break */
74 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
75 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
76 #define UCR1_DOZE (1<<1) /* Doze */
77 #define UCR1_UARTEN (1<<0) /* UART enabled */
79 #define UTS_FRCPERR (1<<13) /* Force parity error */
80 #define UTS_LOOP (1<<12) /* Loop tx and rx */
81 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
82 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
83 #define UTS_TXFULL (1<<4) /* TxFIFO full */
84 #define UTS_RXFULL (1<<3) /* RxFIFO full */
85 #define UTS_SOFTRST (1<<0) /* Software reset */
148 struct imx_uart_data *pd = calloc(1, sizeof(*pd)); in imx_uart_dev_alloc()
169 return -1; in imx_uart_dev_init()