Lines Matching full:1
11 #define CMD_MUX 1
40 #define DIV_PLL2DIVP 1
84 #define MUX_AXI 1
135 #define CLK_MPU_HSE CLKSRC(MUX_MPU, 1)
140 #define CLK_AXI_HSE CLKSRC(MUX_AXI, 1)
144 #define CLK_MLAHBS_HSE CLKSRC(MUX_MLAHB, 1)
149 #define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1)
152 #define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1)
156 #define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1)
160 #define CLK_RTC_LSE CLKSRC(MUX_RTC, 1)
165 #define CLK_MCO1_HSE CLK_SRC(CK_MCO1, 1)
172 #define CLK_MCO2_AXI CLK_SRC(CK_MCO2, 1)
180 #define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1)
185 #define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1)
190 #define CLK_I2C3_PLL4R CLKSRC(MUX_I2C3, 1)
195 #define CLK_I2C4_PLL4R CLKSRC(MUX_I2C4, 1)
200 #define CLK_I2C5_PLL4R CLKSRC(MUX_I2C5, 1)
205 #define CLK_SPI1_PLL3Q CLKSRC(MUX_SPI1, 1)
211 #define CLK_SPI23_PLL3Q CLKSRC(MUX_SPI23, 1)
217 #define CLK_SPI4_PLL4Q CLKSRC(MUX_SPI4, 1)
224 #define CLK_SPI5_PLL4Q CLKSRC(MUX_SPI5, 1)
230 #define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1)
237 #define CLK_UART2_PLL3Q CLKSRC(MUX_UART2, 1)
244 #define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1)
250 #define CLK_UART4_PLL4Q CLKSRC(MUX_UART4, 1)
256 #define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1)
262 #define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1)
268 #define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1)
275 #define CLK_LPTIM2_PLL4Q CLKSRC(MUX_LPTIM2, 1)
281 #define CLK_LPTIM3_PLL4Q CLKSRC(MUX_LPTIM3, 1)
287 #define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1)
294 #define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1)
300 #define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1)
307 #define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1)
312 #define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1)
316 #define CLK_ADC1_CKPER CLKSRC(MUX_ADC1, 1)
320 #define CLK_ADC2_CKPER CLKSRC(MUX_ADC2, 1)
324 #define CLK_SDMMC1_PLL3R CLKSRC(MUX_SDMMC1, 1)
329 #define CLK_SDMMC2_PLL3R CLKSRC(MUX_SDMMC2, 1)
334 #define CLK_ETH1_PLL3Q CLKSRC(MUX_ETH1, 1)
337 #define CLK_ETH2_PLL3Q CLKSRC(MUX_ETH2, 1)
340 #define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1)
344 #define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1)
347 #define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1)
352 #define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1)
357 #define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1)
362 #define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1)
365 #define CLK_DCMIPP_PLL2Q CLKSRC(MUX_DCMIPP, 1)
370 #define CLK_SAES_CKPER CLKSRC(MUX_SAES, 1)
376 #define SSCG_MODE_DOWN_SPREAD 1
380 #define LSEDRV_MEDIUM_LOW 1