Searched +full:0 +full:xc883c000 (Results 1 – 4 of 4) sorted by relevance
64 hwrom_reserved: hwrom@0 {65 reg = <0x0 0x0 0x0 0x1000000>;71 reg = <0x0 0x10000000 0x0 0x200000>;78 size = <0x0 0xbc00000>;79 alignment = <0x0 0x400000>;85 #address-cells = <0x2>;86 #size-cells = <0x0>;88 cpu0: cpu@0 {91 reg = <0x0 0x0>;94 clocks = <&scpi_dvfs 0>;[all …]
10 #define GXBB_PERIPHS_BASE 0xc883440011 #define GXBB_HIU_BASE 0xc883c00012 #define GXBB_ETH_BASE 0xc941000017 /* GPIO registers 0 to 6 */18 #define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))19 #define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)23 #define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)24 #define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)26 #define GXBB_ETH_REG_0_PHY_INTF BIT(0)35 #define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40)[all …]
29 hwrom_reserved: hwrom@0 {30 reg = <0x0 0x0 0x0 0x1000000>;36 reg = <0x0 0x10000000 0x0 0x200000>;42 reg = <0x0 0x05000000 0x0 0x300000>;48 reg = <0x0 0x05300000 0x0 0x2000000>;55 size = <0x0 0x10000000>;56 alignment = <0x0 0x400000>;84 #address-cells = <0x2>;85 #size-cells = <0x0>;87 cpu0: cpu@0 {[all …]
89 port@0:103 const: 0109 - port@0121 reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>;125 #size-cells = <0>;129 port@0 {130 reg = <0>;